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REJ09B0155-0300
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16
H8S/2628 Group
Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series
Rev. 3.00 Revision Date: Oct 04, 2005
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Rev. 3.00 Oct 04, 2005 page ii of xl
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 3.00 Oct 04, 2005 page iii of xl
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. 7. General Precautions on Handling of Product Configuration of This Manual Preface Main Revisions in This Edition Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 8. List of Registers 9. Electrical Characteristics 10. Appendix The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
Rev. 3.00 Oct 04, 2005 page iv of xl
Preface
The H8S/2628 Group are single-chip microcomputers made up of the high-speed H8S/2600 CPU as its core, and the peripheral functions required to configure a system. The H8S/2600 CPU has an instruction set that is compatible with the H8/300 and H8/300H CPUs. This LSI is equipped with a data transfer controller (DTC), ROM and RAM memory, a PC break controller (PBC), a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), a watchdog timer (WDT), a serial communication interface (SCI), a controller area network (HCAN), a synchronous serial communication unit (SSU), an A/D converter, and I/O ports as onchip peripheral modules required for system configuration. This LSI is suitable for use as an embedded microcomputer for high-level control systems. A single-power flash memory (FZTATTM) version is available for this LSI's ROM. This provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Renesas Technology, Corp. Target Users: This manual was written for users who will be using the H8S/2628 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2628 Group to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 22, List of Registers.
Rev. 3.00 Oct 04, 2005 page v of xl
Example:
Register name:
Bit order: Related Manuals:
The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right.
The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/
H8S/2628 Group manuals:
Document Title H8S/2628 Group Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual Document No. This manual REJ09B0139
User's manuals for development tools:
Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop, High-performance Debugging Interface Tutorial High-performance Embedded Workshop User's Manual Document No. REJ10B0058 ADE-702-037 ADE-702-231 ADE-702-201
Rev. 3.00 Oct 04, 2005 page vi of xl
Main Revisions for This Edition
Item 9.6.6 Pin Functions Table 9.27 PA2 Pin Function 10.4.5 PMW Modes 219 Page 148 Revision (See Manual for Details) Table 9.27 amended
RE in SCR_2 PA2DDR Pin function 0 PA2 input 0 1 PA2 output 1
--
RxD2 input
Description amended * PMW mode 2 (Before) ... clearing by a synchronization register compare match ... (After) ... clearing by a duty cycle register compare match ...
15.3 Register Descriptions
373
Description amended (Before) Local acceptance filter mask H (LAFMH) (After) Local acceptance filter mask L (LAFML)
374 15.3.1 Master Control Register (MCR) 375
(Before) Local acceptance filter mask L (LAFML) (After) Local acceptance filter mask H (LAFMH) Description deleted Reset Request ... [Setting condition] * 1-write (software reset) Description amended Transmit/Receive Warning Flag ... [Setting condition] * Third bit of Intermission after EOF (End of Frame) [Clearing condition] * When TEC < 96 and REC < 96 or TEC 256 (bus off state)
15.3.2 General 376 Status Register (GSR)
15.3.11 Interrupt Register (IRR)
387
Description amended Remote Frame Request Interrupt Flag ... in a mailbox (buffer), when MBIMR = 0. Receive Message Interrupt Flag ... received normally, when MBIMR = 0.
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Item 15.3.16 Unread Message Status Register (UMSR)
Page 393
Revision (See Manual for Details) Description amended (Before) [Setting condition] * When a new message is received before RXPR is cleared [Clearing condition] * Writing 1 The received message has been overwritten by a new message before being read. (After) The received message has been overwritten by a new message before being read. [ Setting condition] * When a new message is received before RXPR is cleared [Clearing condition] * Writing 1
15.3.18 Message Control (MC15 to MC0) 15.4.2 Initialization after Hardware Reset Figure 15.8 Detailed Description of One Bit
397
Description amended Data Length Code (Before) 1000: 8 bytes ... 1111: 8 bytes (After) 1***: 8 bytes
403
Figure 15.8 amended
1-bit time (25 to 8 time quanta)
SYNC_SEG
PRSEG
PHSEG1
PHSEG2 Time segment 2 (TSEG2) 2 to 8 time quanta
Time segment 1 (TSEG1) 1 time quanta 4 to 16 time quanta
Table 15.3 Setting 404 Range for TSEG1 and TSEG2 in BCR 15.8.10 HCAN TXCR 420 Operation
Note * amended Note: * Settable when bits BRP is not B000000. Description amended Conditions: * The HRxD pin is stacked to 1 because of ... Countermeasures: * Transmission must not be canceled ... Countermeasure: * A transmit wait message must be ... ... reset for HCAN or HCAN sleep mode (MCR0 = 0 or MCR5 = 0), confirm that ...
Section 16 Synchronous Serial Communication Unit (SSU)
423
Description deleted ... different clock polarity and clock phase. Figure 16.1 is a ...
433 16.3.6 SS transmit Data Register 3 to 0 (SSTDR3 to SSTDR0)
Description amended ... SSTDR0 are valid. Do not attempt to access invalid SS transmit data registers. When the SSU detects ...
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000000
15.8.12 Canceling HCAN Reset and HCAN Sleep Mode
421
Description amended
Item
Page
Revision (See Manual for Details) Description amended ... SSRDR0 are valid. Do not attempt to access invalid SS receive data registers. When the SSU has received ... Figure 16.4 amended
[4] Specify TE, RE, TEIE, TIE, RIE, and CEIE bits simultaneously
16.3.7 SS Receive 434 Data Register 3 to 0 (SSRDR3 to SSRDR0) 16.4.4 Data 437 Transmission and Data Reception Figure 16.4 Example of SSU Initialization
End
438
Description amended Data Transmission (Before) ... data to SSTDR after the TE bit in SSER is set to 1 clears the TDRE bit in SSSR to 0, and the SSTDR contents is transferred to SSTRSR. (After) ... data to SSTDR after initialization of the SSU automatically clears the TDRE bit in SSSR to 0, and the contents of SSTDR is transferred to SSTRSR.
Figure 16.6 Example 440 of Data Transmission Flowchart
Figure 16.6 amended
Start [1] [2] Initialization Read TDRE in SSR
441
Description amended Data Reception (Before) ... After the SSU sets the RE bit in SSER to 1 and dummy-reads SSRDR, data ... (After) ... After initialization, the SSU dummy-reads SSRDR and data ...
Rev. 3.00 Oct 04, 2005 page ix of xl
Item
Page
Revision (See Manual for Details) Figure 16.7 amended
(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0 SCS 1 frame 1 frame
16.4.4 Data 442 Transmission and Data Reception Figure 16.7 Example of Reception Operation
SSCK SSI
Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
SSTDR0 (LSB first transmission)
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 10
SSTDR0 (MSB first transmission)
RDRF LSI operation User operation Dummy-read SSRDR0
RXI interrupt generated RXI interrupt generated
Read SSRDR0
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0 SCS 1 frame
SSCK SSI (LSB first) SSI (MSB first)
Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
SSRDR1
Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
SSRDR0
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0
SSRDR0
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0
SSRDR1
RDRF LSI operation User operation Dummy-read SSRDR0
RXI interrupt generated
(3) When 32-bit data length is selected (SSRDR0, SSRDR1, SSRDR2, and SSRDR3 are valid) with CPOS = 0 and CPHS = 0 SCS
SSCK SSI (LSB first) SSI (MSB first) RDRF LSI operation User operation Dummy-read SSRDR0
RXI interrupt generated Bit 0 to Bit Bit 7 0 to Bit Bit 7 0 to Bit 7 Bit 0 to Bit 7
SSRDR3
SSRDR2
SSRDR1
SSRDR0
Bit 7
to
Bit Bit 0 7
to
Bit 0
Bit 7
to
Bit Bit 0 7
to
Bit 0
SSRDR0
SSRDR1
SSRDR2
SSRDR3
Figure 16.8 Example 443 of Data Reception Flowchart
Figure 16.8 amended
Start [1] [2] Initialization Dummy-read SSRDR
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Item
Page
Revision (See Manual for Details) Figure 16.9 amended
Start [1] [2] Initialization Read TDRE in SSSR
16.4.4 Data 445 Transmission and Data Reception Figure 16.9 Example of Simultaneous Transmission/ Reception Flowchart
Continuous data transmission/reception No Read TEND in SSSR TEND = 1? Yes Clear TEND in SSSR to 0
Yes
No
1-bit internal elapsed? Yes Clear TE and RE in SSER to 0
No Error processing
End transmission/reception Note: Hatching boxes represent SSU internal operations.
16.4.5 pin Control and Conflict Error Figure 16.10 Conflict Error Detection Timing (Before Transfer Start)
446
Description amended (Before) ... (Hi-Z) to detect arbitration. The arbitration detection period ... (After) ...(Hi-Z) to detect conflict error. The conflict detection period ... Figure 16.10 amended (Before) Arbitration detection period (After) Conflict error detection period Figure 16.11 amended (Before) Arbitration detection period (After) Conflict error detection period
Figure 16.11 Conflict 447 Error Detection Timing (After Transfer End)
SCS
Rev. 3.00 Oct 04, 2005 page xi of xl
Item Section 21 PowerDown Modes Table 21.2 LSI Internal States in Each Mode
Page 503
Revision (See Manual for Details) Table 21.2 amended
Function Peripheral functions SCI HCAN A/D MediumHigh-Speed Speed Operate Operate Sleep Operate Module Stop Halted* (reset/ retained) Software Standby Halted (reset) Hardware Standby Halted (reset)
Note * amended Notes: ... has been, made are halted (reset or retained). * The SCI's TDR, RDR, and SSR are halted (reset), and the other registers are halted (retained). 22. 3 Register States 571, 572 in Each Operating Mode Table amended
Register Abbreviation Reset SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized High Speed -- -- -- -- -- -- -- -- -- -- -- -- -- -- Medium Speed -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sleep -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module Stop -- -- -- Initialized Initialized Initialized -- -- -- -- Initialized Initialized Initialized -- Software Standby -- -- -- Initialized Initialized Initialized -- -- -- -- Initialized Initialized Initialized -- Hardware Standby Module Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_2 SCI_0
Section 23 Electrical 573 to 592 "Preliminary" deleted Characteristics Appendix C Package 594 Dimensions Figure C.1 FP-100M Package Dimensions Figure C.1 replaced
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Contents
Section 1 Overview.............................................................................................................
1.1 1.2 1.3 1.4 Overview........................................................................................................................... Internal Block Diagram..................................................................................................... Pin Arrangement............................................................................................................... Pin Functions .................................................................................................................... 1 1 2 3 4
Section 2 CPU ...................................................................................................................... 11
2.1 Features............................................................................................................................. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.2 Differences from H8/300 CPU ............................................................................ 2.1.3 Differences from H8/300H CPU ......................................................................... CPU Operating Modes...................................................................................................... 2.2.1 Normal Mode....................................................................................................... 2.2.2 Advanced Mode................................................................................................... Address Space................................................................................................................... Registers ........................................................................................................................... 2.4.1 General Registers................................................................................................. 2.4.2 Program Counter (PC) ......................................................................................... 2.4.3 Extended Control Register (EXR) ....................................................................... 2.4.4 Condition-Code Register (CCR).......................................................................... 2.4.5 Multiply-Accumulate Register (MAC)................................................................ 2.4.6 Initial Values of CPU Registers........................................................................... Data Formats..................................................................................................................... 2.5.1 General Register Data Formats............................................................................ 2.5.2 Memory Data Formats......................................................................................... Instruction Set................................................................................................................... 2.6.1 Table of Instructions Classified by Function ....................................................... 2.6.2 Basic Instruction Formats .................................................................................... Addressing Modes and Effective Address Calculation..................................................... 2.7.1 Register DirectRn ............................................................................................ 2.7.2 Register Indirect@ERn.................................................................................... 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn).............. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn.. 2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32 ................................... 2.7.6 Immediate#xx:8, #xx:16, or #xx:32................................................................. 2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC) ................................... 2.7.8 Memory Indirect@@aa:8 ................................................................................ 2.7.9 Effective Address Calculation ............................................................................. 11 12 13 13 14 14 15 18 19 20 21 21 22 23 23 24 24 26 27 28 38 39 40 40 40 41 41 42 42 42 43
2.2
2.3 2.4
2.5
2.6
2.7
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2.8 2.9
Processing States .............................................................................................................. 46 Usage Note ....................................................................................................................... 47 2.9.1 Notes on Using the Bit Operation Instruction...................................................... 47
Section 3 MCU Operating Modes .................................................................................. 49
3.1 3.2 Operating Mode Selection ................................................................................................ Register Descriptions........................................................................................................ 3.2.1 Mode Control Register (MDCR) ......................................................................... 3.2.2 System Control Register (SYSCR)...................................................................... Pin Functions in Each Operating Mode ............................................................................ Address Map..................................................................................................................... 49 49 50 51 52 53
3.3 3.4
Section 4 Exception Handling ......................................................................................... 55
4.1 4.2 4.3 Exception Handling Types and Priority............................................................................ Exception Sources and Exception Vector Table............................................................... Reset ................................................................................................................................. 4.3.1 Reset Exception Handling ................................................................................... 4.3.2 Interrupts after Reset............................................................................................ 4.3.3 State of On-Chip Peripheral Modules after Reset Release .................................. Traces................................................................................................................................ Interrupts........................................................................................................................... Trap Instruction ................................................................................................................ Stack Status after Exception Handling.............................................................................. Usage Note ....................................................................................................................... 55 55 57 57 59 60 60 61 62 63 64
4.4 4.5 4.6 4.7 4.8
Section 5 Interrupt Controller .......................................................................................... 65
5.1 5.2 5.3 Features............................................................................................................................. Input/Output Pins.............................................................................................................. Register Descriptions........................................................................................................ 5.3.1 Interrupt Priority Registers A to M (IPRA to IPRM) .......................................... 5.3.2 IRQ Enable Register (IER) .................................................................................. 5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.3.4 IRQ Status Register (ISR).................................................................................... Interrupt Sources............................................................................................................... 5.4.1 External Interrupts ............................................................................................... 5.4.2 Internal Interrupts ................................................................................................ Interrupt Exception Handling Vector Table...................................................................... Interrupt Control Modes and Interrupt Operation............................................................. 5.6.1 Interrupt Control Mode 0..................................................................................... 5.6.2 Interrupt Control Mode 2..................................................................................... 5.6.3 Interrupt Exception Handling Sequence .............................................................. 65 67 67 68 69 70 72 73 73 74 74 78 78 80 81
5.4
5.5 5.6
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5.7
5.6.4 Interrupt Response Times .................................................................................... 5.6.5 DTC Activation by Interrupt................................................................................ Usage Notes ...................................................................................................................... 5.7.1 Conflict between Interrupt Generation and Disabling ......................................... 5.7.2 Instructions that Disable Interrupts...................................................................... 5.7.3 When Interrupts Are Disabled ............................................................................. 5.7.4 Interrupts during Execution of EEPMOV Instruction ......................................... 5.7.5 IRQ Interrupt .......................................................................................................
83 84 84 84 85 85 86 86
Section 6 PC Break Controller (PBC)........................................................................... 87
6.1 6.2 Features............................................................................................................................. Register Descriptions........................................................................................................ 6.2.1 Break Address Register A (BARA) ..................................................................... 6.2.2 Break Address Register B (BARB) ..................................................................... 6.2.3 Break Control Register A (BCRA) ...................................................................... 6.2.4 Break Control Register B (BCRB) ...................................................................... Operation .......................................................................................................................... 6.3.1 PC Break Interrupt Due to Instruction Fetch ....................................................... 6.3.2 PC Break Interrupt Due to Data Access .............................................................. 6.3.3 PC Break Operation at Consecutive Data Transfer ............................................. 6.3.4 Operation in Transitions to Power-Down Modes ................................................ 6.3.5 When Instruction Execution Is Delayed by One State......................................... Usage Notes ...................................................................................................................... 6.4.1 Module Stop Mode Setting .................................................................................. 6.4.2 PC Break Interrupts ............................................................................................. 6.4.3 CMFA and CMFB ............................................................................................... 6.4.4 PC Break Interrupt when DTC Is Bus Master ..................................................... 6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction....................................................................... 6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction ....................................... 6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction.......... 6.4.8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc Instruction............................................................................................................ 87 88 88 89 89 90 90 90 91 91 91 92 93 93 93 93 93 93 93 94 94
6.3
6.4
Section 7 Bus Controller ................................................................................................... 95
7.1 Basic Timing..................................................................................................................... 7.1.1 On-Chip Memory Access Timing (ROM, RAM)................................................ 7.1.2 On-Chip Support Module Access Timing ........................................................... 7.1.3 On-Chip HCAN Module Access Timing............................................................. 7.1.4 On-Chip SSU Module and Realtime Input Port Data Register Access Timing ... Bus Arbitration ................................................................................................................. 95 95 96 97 98 99
7.2
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7.2.1 7.2.2
Order of Priority of the Bus Masters.................................................................... 99 Bus Transfer Timing............................................................................................ 99
Section 8 Data Transfer Controller (DTC)................................................................... 101
8.1 8.2 Features............................................................................................................................. Register Descriptions........................................................................................................ 8.2.1 DTC Mode Register A (MRA) ............................................................................ 8.2.2 DTC Mode Register B (MRB)............................................................................. 8.2.3 DTC Source Address Register (SAR).................................................................. 8.2.4 DTC Destination Address Register (DAR).......................................................... 8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 8.2.6 DTC Transfer Count Register B (CRB)............................................................... 8.2.7 DTC Enable Registers (DTCER)......................................................................... 8.2.8 DTC Vector Register (DTVECR)........................................................................ Activation Sources............................................................................................................ Location of Register Information and DTC Vector Table ................................................ Operation .......................................................................................................................... 8.5.1 Normal Mode....................................................................................................... 8.5.2 Repeat Mode........................................................................................................ 8.5.3 Block Transfer Mode........................................................................................... 8.5.4 Chain Transfer ..................................................................................................... 8.5.5 Interrupts.............................................................................................................. 8.5.6 Operation Timing................................................................................................. 8.5.7 Number of DTC Execution States ....................................................................... Procedures for Using DTC ............................................................................................... 8.6.1 Activation by Interrupt ........................................................................................ 8.6.2 Activation by Software ........................................................................................ Examples of Use of the DTC ............................................................................................ 8.7.1 Normal Mode....................................................................................................... 8.7.2 Chain Transfer ..................................................................................................... 8.7.3 Software Activation ............................................................................................. Usage Notes ...................................................................................................................... 8.8.1 Module Stop Mode Setting .................................................................................. 8.8.2 On-Chip RAM ..................................................................................................... 8.8.3 DTCE Bit Setting................................................................................................. 101 103 104 105 105 105 105 106 106 107 108 109 112 113 114 115 117 118 118 119 121 121 121 122 122 123 124 125 125 125 125
8.3 8.4 8.5
8.6
8.7
8.8
Section 9 I/O Ports .............................................................................................................. 127
9.1 Port 1................................................................................................................................. 9.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 9.1.2 Port 1 Data Register (P1DR) ............................................................................... 9.1.3 Port 1 Register (PORT1) ..................................................................................... 131 131 132 132
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9.2
9.3 9.4
9.5 9.6
9.7
9.8
9.9
9.1.4 Pin Functions ....................................................................................................... Port 3................................................................................................................................. 9.2.1 Port 3 Data Direction Register (P3DDR)............................................................. 9.2.2 Port 3 Data Register (P3DR) ............................................................................... 9.2.3 Port 3 Register (PORT3) ..................................................................................... 9.2.4 Port 3 Open-Drain Control Register (P3ODR) .................................................... 9.2.5 Pin Functions ....................................................................................................... Port 4................................................................................................................................. 9.3.1 Port 4 Register (PORT4) ..................................................................................... Port 7................................................................................................................................. 9.4.1 Port 7 Data Direction Register (P7DDR)............................................................. 9.4.2 Port 7 Data Register (P7DR) ............................................................................... 9.4.3 Port 7 Register (PORT7) ..................................................................................... 9.4.4 Pin Functions ....................................................................................................... Port 9................................................................................................................................. 9.5.1 Port 9 Register (PORT9) ..................................................................................... Port A................................................................................................................................ 9.6.1 Port A Data Direction Register (PADDR)........................................................... 9.6.2 Port A Data Register (PADR).............................................................................. 9.6.3 Port A Register (PORTA).................................................................................... 9.6.4 Port A Pull-Up MOS Control Register (PAPCR)................................................ 9.6.5 Port A Open-Drain Control Register (PAODR) .................................................. 9.6.6 Pin Functions ....................................................................................................... Port B................................................................................................................................ 9.7.1 Port B Data Direction Register (PBDDR) ........................................................... 9.7.2 Port B Data Register (PBDR) .............................................................................. 9.7.3 Port B Register (PORTB) .................................................................................... 9.7.4 Port B Pull-Up MOS Control Register (PBPCR) ................................................ 9.7.5 Port B Open-Drain Control Register (PBODR)................................................... 9.7.6 Pin Functions ....................................................................................................... Port C................................................................................................................................ 9.8.1 Port C Data Direction Register (PCDDR) ........................................................... 9.8.2 Port C Data Register (PCDR) .............................................................................. 9.8.3 Port C Register (PORTC) .................................................................................... 9.8.4 Port C Pull-Up MOS Control Register (PCPCR) ................................................ 9.8.5 Port C Open-Drain Control Register (PCODR)................................................... 9.8.6 Pin Functions ....................................................................................................... Port D................................................................................................................................ 9.9.1 Port D Data Direction Register (PDDDR)........................................................... 9.9.2 Port D Data Register (PDDR).............................................................................. 9.9.3 Port D Register (PORTD)....................................................................................
133 136 136 137 137 138 138 140 140 140 141 141 142 142 144 144 145 145 146 146 147 147 148 149 149 150 150 151 151 152 154 154 155 155 156 156 157 160 160 161 161
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9.9.4 Port D Pull-Up MOS Control Register (PDPCR)................................................ 9.9.5 Port D RealTime Input Data Register (PDRTIDR) ............................................. 9.10 Port F ................................................................................................................................ 9.10.1 Port F Data Direction Register (PFDDR) ............................................................ 9.10.2 Port F Data Register (PFDR) ............................................................................... 9.10.3 Port F Register (PORTF) ..................................................................................... 9.10.4 Pin Functions .......................................................................................................
162 162 163 163 164 164 165
Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 167 10.1 Features............................................................................................................................. 167 10.2 Input/Output Pins.............................................................................................................. 171 10.3 Register Descriptions........................................................................................................ 172 10.3.1 Timer Control Register (TCR)............................................................................. 174 10.3.2 Timer Mode Register (TMDR)............................................................................ 179 10.3.3 Timer I/O Control Register (TIOR)..................................................................... 181 10.3.4 Timer Interrupt Enable Register (TIER).............................................................. 198 10.3.5 Timer Status Register (TSR)................................................................................ 200 10.3.6 Timer Counter (TCNT)........................................................................................ 203 10.3.7 Timer General Register (TGR) ............................................................................ 203 10.3.8 Timer Start Register (TSTR) ............................................................................... 203 10.3.9 Timer Synchro Register (TSYR) ......................................................................... 204 10.4 Operation .......................................................................................................................... 205 10.4.1 Basic Functions.................................................................................................... 205 10.4.2 Synchronous Operation ....................................................................................... 211 10.4.3 Buffer Operation.................................................................................................. 212 10.4.4 Cascaded Operation ............................................................................................. 217 10.4.5 PWM Modes........................................................................................................ 219 10.4.6 Phase Counting Mode.......................................................................................... 224 10.5 Interrupt Sources............................................................................................................... 231 10.6 DTC Activation ................................................................................................................ 233 10.7 A/D Converter Activation................................................................................................. 233 10.8 Operation Timing.............................................................................................................. 234 10.8.1 Input/Output Timing............................................................................................ 234 10.8.2 Interrupt Signal Timing ....................................................................................... 237 10.9 Usage Notes ...................................................................................................................... 241 10.9.1 Module Stop Mode Setting .................................................................................. 241 10.9.2 Input Clock Restrictions ...................................................................................... 241 10.9.3 Caution on Period Setting.................................................................................... 242 10.9.4 Conflict between TCNT Write and Clear Operations ......................................... 242 10.9.5 Conflict between TCNT Write and Increment Operations .................................. 243 10.9.6 Conflict between TGR Write and Compare Match ............................................. 244
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10.9.7 Conflict between Buffer Register Write and Compare Match............................. 10.9.8 Conflict between TGR Read and Input Capture .................................................. 10.9.9 Conflict between TGR Write and Input Capture ................................................. 10.9.10 Conflict between Buffer Register Write and Input Capture................................. 10.9.11 Conflict between Overflow/Underflow and Counter Clearing ............................ 10.9.12 Conflict between TCNT Write and Overflow/Underflow ................................... 10.9.13 Multiplexing of I/O Pins...................................................................................... 10.9.14 Interrupts in Module Stop Mode..........................................................................
245 246 247 248 249 250 250 250
Section 11 8-Bit Timers..................................................................................................... 251 11.1 Features............................................................................................................................. 251 11.2 Input/Output Pins.............................................................................................................. 253 11.3 Register Descriptions........................................................................................................ 253 11.3.1 Timer Counters (TCNT) ...................................................................................... 254 11.3.2 Time Constant Registers A (TCORA)................................................................. 254 11.3.3 Time Constant Registers B (TCORB) ................................................................. 254 11.3.4 Timer Control Registers (TCR) ........................................................................... 255 11.3.5 Timer Control/Status Registers (TCSR) .............................................................. 257 11.4 Operation .......................................................................................................................... 262 11.4.1 Pulse Output ........................................................................................................ 262 11.5 Operation Timing.............................................................................................................. 263 11.5.1 TCNT Incrementation Timing ............................................................................. 263 11.5.2 Timing of CMFA and CMFB Setting When a Compare-Match Occurs ............. 264 11.5.3 Timing of Timer Output When a Compare-Match Occurs.................................. 264 11.5.4 Timing of Compare-Match Clear When a Compare-Match Occurs .................... 265 11.5.5 TCNT External Reset Timing.............................................................................. 265 11.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 266 11.6 Operation with Cascaded Connection............................................................................... 267 11.6.1 16-Bit Count Mode .............................................................................................. 267 11.6.2 Compare-Match Count Mode .............................................................................. 267 11.7 Interrupt Sources............................................................................................................... 268 11.7.1 Interrupt Sources and DTC Activation ................................................................ 268 11.7.2 A/D Converter Activation.................................................................................... 268 11.8 Usage Notes ...................................................................................................................... 269 11.8.1 Conflict between TCNT Write and Clear ............................................................ 269 11.8.2 Conflict between TCNT Write and Increment..................................................... 270 11.8.3 Conflict between TCOR Write and Compare-Match........................................... 271 11.8.4 Conflict between Compare-Matches A and B ..................................................... 271 11.8.5 Switching of Internal Clocks and TCNT Operation ............................................ 272 11.8.6 Conflict between Interrupts and Module Stop Mode........................................... 273 11.8.7 Notes on Cascaded Connection ........................................................................... 273
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Section 12 Programmable Pulse Generator (PPG) .................................................... 275 12.1 Features............................................................................................................................. 275 12.2 Input/Output Pins.............................................................................................................. 277 12.3 Register Descriptions........................................................................................................ 277 12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ........................................ 278 12.3.2 Output Data Registers H, L (PODRH, PODRL) ................................................. 279 12.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 280 12.3.4 PPG Output Control Register (PCR) ................................................................... 282 12.3.5 PPG Output Mode Register (PMR) ..................................................................... 283 12.4 Operation .......................................................................................................................... 284 12.4.1 Overview.............................................................................................................. 284 12.4.2 Output Timing ..................................................................................................... 285 12.4.3 Sample Setup Procedure for Normal Pulse Output.............................................. 286 12.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 287 12.4.5 Non-Overlapping Pulse Output ........................................................................... 288 12.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output.............................. 290 12.4.7 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) ......................................................... 291 12.4.8 Inverted Pulse Output .......................................................................................... 293 12.4.9 Pulse Output Triggered by Input Capture............................................................ 294 12.5 Usage Notes ...................................................................................................................... 294 12.5.1 Module Stop Mode Setting .................................................................................. 294 12.5.2 Operation of Pulse Output Pins ........................................................................... 294 Section 13 Watchdog Timer............................................................................................. 295 13.1 Features............................................................................................................................. 295 13.2 Register Descriptions........................................................................................................ 296 13.2.1 Timer Counter (TCNT)........................................................................................ 296 13.2.2 Timer Control/Status Register (TCSR)................................................................ 297 13.2.3 Reset Control/Status Register (RSTCSR)............................................................ 299 13.3 Operation .......................................................................................................................... 300 13.3.1 Watchdog Timer Mode Operation ....................................................................... 300 13.3.2 Interval Timer Mode............................................................................................ 300 13.4 Interrupts........................................................................................................................... 301 13.5 Usage Notes ...................................................................................................................... 301 13.5.1 Notes on Register Access .................................................................................... 301 13.5.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 302 13.5.3 Changing Value of CKS2 to CKS0 ..................................................................... 303 13.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 303 13.5.5 Internal Reset in Watchdog Timer Mode............................................................. 303 13.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 303
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Section 14 Serial Communication Interface (SCI) .................................................... 305 14.1 Features............................................................................................................................. 305 14.2 Input/Output Pins.............................................................................................................. 307 14.3 Register Descriptions........................................................................................................ 307 14.3.1 Receive Shift Register (RSR) .............................................................................. 308 14.3.2 Receive Data Register (RDR).............................................................................. 308 14.3.3 Transmit Data Register (TDR) ............................................................................ 308 14.3.4 Transmit Shift Register (TSR)............................................................................. 308 14.3.5 Serial Mode Register (SMR) ............................................................................... 309 14.3.6 Serial Control Register (SCR) ............................................................................. 313 14.3.7 Serial Status Register (SSR) ................................................................................ 316 14.3.8 Smart Card Mode Register (SCMR).................................................................... 322 14.3.9 Bit Rate Register (BRR) ...................................................................................... 323 14.4 Operation in Asynchronous Mode .................................................................................... 330 14.4.1 Data Transfer Format........................................................................................... 330 14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 332 14.4.3 Clock.................................................................................................................... 333 14.4.4 SCI Initialization (Asynchronous Mode)............................................................. 334 14.4.5 Data Transmission (Asynchronous Mode) .......................................................... 335 14.4.6 Serial Data Reception (Asynchronous Mode) ..................................................... 337 14.5 Multiprocessor Communication Function ........................................................................ 341 14.5.1 Multiprocessor Serial Data Transmission............................................................ 342 14.5.2 Multiprocessor Serial Data Reception ................................................................. 343 14.6 Operation in Clocked Synchronous Mode ........................................................................ 347 14.6.1 Clock.................................................................................................................... 347 14.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 348 14.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 349 14.6.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 352 14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) .................................................................................................................. 354 14.7 Operation in Smart Card Interface.................................................................................... 356 14.7.1 Pin Connection Example ..................................................................................... 356 14.7.2 Data Format (Except for Block Transfer Mode).................................................. 357 14.7.3 Block Transfer Mode........................................................................................... 359 14.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode.................................................................................................................... 359 14.7.5 Initialization......................................................................................................... 360 14.7.6 Data Transmission (Except for Block Transfer Mode)........................................ 361 14.7.7 Serial Data Reception (Except for Block Transfer Mode)................................... 364 14.7.8 Clock Output Control .......................................................................................... 366 14.8 Interrupt Sources............................................................................................................... 368
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14.8.1 Interrupts in Normal Serial Communication Interface Mode .............................. 14.8.2 Interrupts in Smart Card Interface Mode ............................................................. 14.9 Usage Notes ...................................................................................................................... 14.9.1 Module Stop Mode Setting .................................................................................. 14.9.2 Break Detection and Processing .......................................................................... 14.9.3 Mark State and Break Detection.......................................................................... 14.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)....................................................................................................................
368 369 370 370 370 370 370
Section 15 Controller Area Network (HCAN) ........................................................... 371 15.1 Features............................................................................................................................. 371 15.2 Input/Output Pins.............................................................................................................. 373 15.3 Register Descriptions........................................................................................................ 373 15.3.1 Master Control Register (MCR) .......................................................................... 374 15.3.2 General Status Register (GSR) ............................................................................ 375 15.3.3 Bit Configuration Register (BCR) ....................................................................... 377 15.3.4 Mailbox Configuration Register (MBCR) ........................................................... 379 15.3.5 Transmit Wait Register (TXPR) .......................................................................... 380 15.3.6 Transmit Wait Cancel Register (TXCR).............................................................. 381 15.3.7 Transmit Acknowledge Register (TXACK) ........................................................ 382 15.3.8 Abort Acknowledge Register (ABACK) ............................................................. 383 15.3.9 Receive Complete Register (RXPR).................................................................... 384 15.3.10 Remote Request Register (RFPR) ....................................................................... 385 15.3.11 Interrupt Register (IRR)....................................................................................... 386 15.3.12 Mailbox Interrupt Mask Register (MBIMR) ....................................................... 390 15.3.13 Interrupt Mask Register (IMR) ............................................................................ 391 15.3.14 Receive Error Counter (REC).............................................................................. 392 15.3.15 Transmit Error Counter (TEC) ............................................................................ 392 15.3.16 Unread Message Status Register (UMSR)........................................................... 393 15.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 394 15.3.18 Message Control (MC15 to MC0) ....................................................................... 396 15.3.19 Message Data (MD15 to MD0) ........................................................................... 398 15.3.20 HCAN Monitor Register (HCANMON) ............................................................. 399 15.4 Operation .......................................................................................................................... 400 15.4.1 Hardware and Software Resets ............................................................................ 400 15.4.2 Initialization after Hardware Reset ...................................................................... 400 15.4.3 Message Transmission......................................................................................... 405 15.4.4 Message Reception .............................................................................................. 409 15.4.5 HCAN Sleep Mode.............................................................................................. 412 15.4.6 HCAN Halt Mode................................................................................................ 415 15.5 Interrupt Sources............................................................................................................... 416
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15.6 DTC Interface ................................................................................................................... 15.7 CAN Bus Interface ........................................................................................................... 15.8 Usage Notes ...................................................................................................................... 15.8.1 Module Stop Mode Setting .................................................................................. 15.8.2 Reset .................................................................................................................... 15.8.3 HCAN Sleep Mode.............................................................................................. 15.8.4 Interrupts.............................................................................................................. 15.8.5 Error Counters ..................................................................................................... 15.8.6 Register Access.................................................................................................... 15.8.7 HCAN Medium-Speed Mode .............................................................................. 15.8.8 Register Hold in Standby Modes ......................................................................... 15.8.9 Use on Bit Manipulation Instructions .................................................................. 15.8.10 HCAN TXCR Operation ..................................................................................... 15.8.11 HCAN Transmit Procedure ................................................................................. 15.8.12 Canceling HCAN Reset and HCAN Sleep Mode................................................ 15.8.13 Accessing Mailbox in HCAN Sleep Mode..........................................................
417 418 418 418 418 419 419 419 419 419 419 419 420 421 421 421
Section 16 Synchronous Serial Communication Unit (SSU) ................................. 423 16.1 Features............................................................................................................................. 423 16.2 Input/Output Pins.............................................................................................................. 425 16.3 Register Descriptions........................................................................................................ 425 16.3.1 SS Control Register H (SSCRH) ......................................................................... 426 16.3.2 SS Control Register L (SSCRL) .......................................................................... 428 16.3.3 SS Mode Register (SSMR) .................................................................................. 429 16.3.4 SS Enable Register (SSER) ................................................................................. 430 16.3.5 SS Status Register (SSSR)................................................................................... 431 16.3.6 SS Transmit Data Register 3 to 0 (SSTDR3 to SSTDR0) ................................... 433 16.3.7 SS Receive Data Register 3 to 0 (SSRDR3 to SSRDR0) .................................... 434 16.3.8 SS Shift Register (SSTRSR)................................................................................ 434 16.4 Operation .......................................................................................................................... 435 16.4.1 Transfer Clock ..................................................................................................... 435 16.4.2 Relationship of Clock Phase, Polarity, and Data ................................................. 435 16.4.3 Relationship between Data I/O Pins and the Shift Register................................. 436 16.4.4 Data Transmission and Data Reception............................................................... 437 16.4.5 Pin Control and Conflict Error .................................................................... 446 16.5 Interrupt Requests............................................................................................................. 447 16.6 Usage Note ....................................................................................................................... 448 16.6.1 Setting of Module Stop Mode.............................................................................. 448 Section 17 A/D Converter................................................................................................. 449
17.1 Features............................................................................................................................. 449
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SCS
17.2 Input/Output Pins.............................................................................................................. 17.3 Register Description ......................................................................................................... 17.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 17.3.2 A/D Control/Status Register (ADCSR) ............................................................... 17.3.3 A/D Control Register (ADCR) ............................................................................ 17.4 Operation .......................................................................................................................... 17.4.1 Single Mode......................................................................................................... 17.4.2 Scan Mode ........................................................................................................... 17.4.3 Input Sampling and A/D Conversion Time ......................................................... 17.4.4 External Trigger Input Timing............................................................................. 17.5 Interrupt Source ................................................................................................................ 17.6 A/D Conversion Accuracy Definitions ............................................................................. 17.7 Usage Notes ...................................................................................................................... 17.7.1 Module Stop Mode Setting .................................................................................. 17.7.2 Permissible Signal Source Impedance ................................................................. 17.7.3 Influences on Absolute Accuracy ........................................................................ 17.7.4 Range of Analog Power Supply and Other Pin Settings...................................... 17.7.5 Notes on Board Design ........................................................................................ 17.7.6 Notes on Noise Countermeasures ........................................................................
451 452 452 453 455 456 456 456 457 459 459 460 462 462 462 462 463 463 463
Section 18 RAM .................................................................................................................. 465 Section 19 ROM .................................................................................................................. 467
Features............................................................................................................................. Mode Transitions .............................................................................................................. Block Configuration ......................................................................................................... Input/Output Pins.............................................................................................................. Register Descriptions........................................................................................................ 19.5.1 Flash Memory Control Register 1 (FLMCR1) .................................................... 19.5.2 Flash Memory Control Register 2 (FLMCR2) .................................................... 19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 19.5.5 RAM Emulation Register (RAMER)................................................................... 19.6 On-Board Programming Modes........................................................................................ 19.6.1 Boot Mode ........................................................................................................... 19.6.2 Programming/Erasing in User Program Mode..................................................... 19.7 Flash Memory Emulation in RAM ................................................................................... 19.8 Flash Memory Programming/Erasing............................................................................... 19.8.1 Program/Program-Verify..................................................................................... 19.8.2 Erase/Erase-Verify............................................................................................... 19.8.3 Interrupt Handling when Programming/Erasing Flash Memory..........................
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19.1 19.2 19.3 19.4 19.5
467 468 472 473 473 473 475 475 476 476 477 478 480 482 484 484 486 486
19.9 Program/Erase Protection ................................................................................................. 19.9.1 Hardware Protection ............................................................................................ 19.9.2 Software Protection ............................................................................................. 19.9.3 Error Protection ................................................................................................... 19.10 Programmer Mode ............................................................................................................ 19.11 Power-Down States for Flash Memory............................................................................. 19.12 Note on Switching from F-ZTAT Version to Masked ROM Version ..............................
488 488 488 488 489 489 490 491 492 492 493 494 494 495 497 497 497 498 498 498
Section 20 Clock Pulse Generator .................................................................................. 20.1 Register Descriptions........................................................................................................ 20.1.1 System Clock Control Register (SCKCR) ........................................................... 20.1.2 Low-Power Control Register (LPWRCR) ........................................................... 20.2 Oscillator .......................................................................................................................... 20.2.1 Connecting a Crystal Resonator .......................................................................... 20.2.2 External Clock Input............................................................................................ 20.3 PLL Circuit ....................................................................................................................... 20.4 Medium-Speed Clock Divider .......................................................................................... 20.5 Bus Master Clock Selection Circuit.................................................................................. 20.6 Usage Notes ...................................................................................................................... 20.6.1 Note on Crystal Resonator................................................................................... 20.6.2 Note on Board Design..........................................................................................
21.1 Register Descriptions........................................................................................................ 21.1.1 Standby Control Register (SBYCR) .................................................................... 21.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC) .................. 21.2 Medium-Speed Mode ....................................................................................................... 21.3 Sleep Mode ....................................................................................................................... 21.3.1 Transition to Sleep Mode..................................................................................... 21.3.2 Clearing Sleep Mode ........................................................................................... 21.4 Software Standby Mode.................................................................................................... 21.4.1 Transition to Software Standby Mode ................................................................. 21.4.2 Clearing Software Standby Mode........................................................................ 21.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 21.4.4 Software Standby Mode Application Example.................................................... 21.5 Hardware Standby Mode .................................................................................................. 21.5.1 Transition to Hardware Standby Mode................................................................ 21.5.2 Clearing Hardware Standby Mode ...................................................................... 21.5.3 Hardware Standby Mode Timings ....................................................................... 21.6 Module Stop Mode ........................................................................................................... 21.7 Clock Output Disabling Function ..................................................................................
Section 21 Power-Down Modes...................................................................................... 501
504 504 506 507 508 508 508 509 509 509 510 511 512 512 512 512 513 514
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21.8 Usage Notes ...................................................................................................................... 21.8.1 I/O Port Status ..................................................................................................... 21.8.2 Current Consumption during Oscillation Stabilization Wait Period.................... 21.8.3 DTC Module Stop ............................................................................................... 21.8.4 On-Chip Peripheral Module Interrupt.................................................................. 21.8.5 Writing to MSTPCR ............................................................................................
515 515 515 515 515 515
Section 22 List of Registers.............................................................................................. 517
22.1 Register Addresses (Address Order)................................................................................. 518 22.2 Register Bits ..................................................................................................................... 536 22.3 Register States in Each Operating Mode .......................................................................... 556
Section 23 Electrical Characteristics ............................................................................. 23.1 Absolute Maximum Ratings ............................................................................................. 23.2 DC Characteristics ............................................................................................................ 23.3 AC Characteristics ............................................................................................................ 23.3.1 Clock Timing ....................................................................................................... 23.3.2 Control Signal Timing ......................................................................................... 23.3.3 Timing of On-Chip Peripheral Modules .............................................................. 23.4 A/D Conversion Characteristics ....................................................................................... 23.5 Flash Memory Characteristics ..........................................................................................
A. B. C.
573 573 574 576 577 578 580 589 590
Appendix.................................................................................................................................. 593
I/O Port States in Each Pin State....................................................................................... 593 Product Code Lineup ........................................................................................................ 594 Package Dimensions ......................................................................................................... 594
Index .......................................................................................................................................... 595
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Figures
Section 1 Overview Figure 1.1 Internal Block Diagram ....................................................................................... Figure 1.2 Pin Arrangement.................................................................................................. Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) ............................................................. Figure 2.2 Stack Structure in Normal Mode ......................................................................... Figure 2.3 Exception Vector Table (Advanced Mode) ......................................................... Figure 2.4 Stack Structure in Advanced Mode ..................................................................... Figure 2.5 Memory Map ....................................................................................................... Figure 2.6 CPU Registers...................................................................................................... Figure 2.7 Usage of General Registers.................................................................................. Figure 2.8 Stack .................................................................................................................... Figure 2.9 General Register Data Formats (1) ...................................................................... Figure 2.9 General Register Data Formats (2) ...................................................................... Figure 2.10 Memory Data Formats......................................................................................... Figure 2.11 Instruction Formats (Examples)........................................................................... Figure 2.12 Branch Address Specification in Memory Indirect Mode ................................... Figure 2.13 State Transitions ..................................................................................................
2 3
15 15 16 17 18 19 20 21 24 25 26 39 43 47
Section 3 MCU Operating Modes Figure 3.1 Address Map........................................................................................................ 53 Section 4 Exception Handling Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled) ....................... Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled: Not Available in this LSI).................................................................................... Figure 4.3 Stack Status after Exception Handling................................................................. Figure 4.4 Operation when SP Value Is Odd ........................................................................ Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller ................................................................ Figure 5.2 Block Diagram of Interrupts IRQ5 to IRQ0 ........................................................ Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2............. Figure 5.5 Interrupt Exception Handling .............................................................................. Figure 5.6 Conflict between Interrupt Generation and Disabling .........................................
58 59 63 64
66 73 79 81 82 85
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Section 6 PC Break Controller (PBC) Figure 6.1 Block Diagram of PC Break Controller............................................................... 88 Figure 6.2 Operation in Power-Down Mode Transitions...................................................... 92 Section 7 Bus Controller Figure 7.1 On-Chip Memory Access Cycle .......................................................................... Figure 7.2 On-Chip Support Module Access Cycle.............................................................. Figure 7.3 On-Chip HCAN Module Access Cycle (with Wait States) ................................. Figure 7.4 On-Chip SSU Module Access Cycle ................................................................... Section 8 Data Transfer Controller (DTC) Figure 8.1 Block Diagram of DTC ....................................................................................... Figure 8.2 Block Diagram of DTC Activation Source Control............................................. Figure 8.3 Location of DTC Register Information in Address Space ................................... Figure 8.4 Flowchart of DTC Operation............................................................................... Figure 8.5 Memory Mapping in Normal Mode..................................................................... Figure 8.6 Memory Mapping in Repeat Mode...................................................................... Figure 8.7 Memory Mapping in Block Transfer Mode......................................................... Figure 8.8 Chain Transfer Operation .................................................................................... Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)................ Figure 8.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) ........................................................................................... Figure 8.11 DTC Operation Timing (Example of Chain Transfer)......................................... Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.1 Block Diagram of TPU........................................................................................ Figure 10.2 Example of Counter Operation Setting Procedure............................................... Figure 10.3 Free-Running Counter Operation ........................................................................ Figure 10.4 Periodic Counter Operation ................................................................................. Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match .......... Figure 10.6 Example of 0 Output/1 Output Operation............................................................ Figure 10.7 Example of Toggle Output Operation.................................................................. Figure 10.8 Example of Input Capture Operation Setting Procedure...................................... Figure 10.9 Example of Input Capture Operation................................................................... Figure 10.10 Example of Synchronous Operation Setting Procedure....................................... Figure 10.11 Example of Synchronous Operation .................................................................... Figure 10.12 Compare Match Buffer Operation ....................................................................... Figure 10.13 Input Capture Buffer Operation........................................................................... Figure 10.14 Example of Buffer Operation Setting Procedure ................................................. Figure 10.15 Example of Buffer Operation (1)......................................................................... Figure 10.16 Example of Buffer Operation (2).........................................................................
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95 96 97 98
102 108 109 112 113 114 116 117 118 119 119
170 205 206 207 207 208 208 209 210 211 212 213 213 214 215 216
Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Figure 10.22 Figure 10.23 Figure 10.24 Figure 10.25 Figure 10.26 Figure 10.27 Figure 10.28 Figure 10.29 Figure 10.30 Figure 10.31 Figure 10.32 Figure 10.33 Figure 10.34 Figure 10.35 Figure 10.36 Figure 10.37 Figure 10.38 Figure 10.39 Figure 10.40 Figure 10.41 Figure 10.42 Figure 10.43 Figure 10.44 Figure 10.45 Figure 10.46 Figure 10.47 Figure 10.48 Figure 10.49 Figure 10.50 Figure 10.51 Figure 10.52 Figure 10.53
Cascaded Operation Setting Procedure................................................................ Example of Cascaded Operation (1) .................................................................... Example of Cascaded Operation (2) .................................................................... Example of PWM Mode Setting Procedure......................................................... Example of PWM Mode Operation (1) ............................................................... Example of PWM Mode Operation (2) ............................................................... Example of PWM Mode Operation (3) ............................................................... Example of Phase Counting Mode Setting Procedure ......................................... Example of Phase Counting Mode 1 Operation................................................... Example of Phase Counting Mode 2 Operation................................................... Example of Phase Counting Mode 3 Operation................................................... Example of Phase Counting Mode 4 Operation................................................... Phase Counting Mode Application Example ....................................................... Count Timing in Internal Clock Operation .......................................................... Count Timing in External Clock Operation......................................................... Output Compare Output Timing.......................................................................... Input Capture Input Signal Timing ...................................................................... Counter Clear Timing (Compare Match)............................................................. Counter Clear Timing (Input Capture) ................................................................ Buffer Operation Timing (Compare Match)........................................................ Buffer Operation Timing (Input Capture)............................................................ TGI Interrupt Timing (Compare Match).............................................................. TGI Interrupt Timing (Input Capture) ................................................................. TCIV Interrupt Setting Timing ............................................................................ TCIU Interrupt Setting Timing ............................................................................ Timing for Status Flag Clearing by CPU............................................................. Timing for Status Flag Clearing by DTC Activation........................................... Phase Difference, Overlap, and Pulse Width in Phase Counting Mode............... Conflict between TCNT Write and Clear Operations.......................................... Conflict between TCNT Write and Increment Operations .................................. Conflict between TGR Write and Compare Match ............................................. Conflict between Buffer Register Write and Compare Match............................. Conflict between TGR Read and Input Capture .................................................. Conflict between TGR Write and Input Capture ................................................. Conflict between Buffer Register Write and Input Capture................................. Conflict between Overflow and Counter Clearing............................................... Conflict between TCNT Write and Overflow......................................................
217 218 218 221 221 222 223 224 225 226 227 228 230 234 234 235 235 236 236 237 237 238 238 239 239 240 240 241 242 243 244 245 246 247 248 249 250
Section 11 8-Bit Timers Figure 11.1 Block Diagram of 8-Bit Timer Module ............................................................... 252 Figure 11.2 Example of Pulse Output ..................................................................................... 262
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Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Figure 11.9 Figure 11.10 Figure 11.11 Figure 11.12
Count Timing for Internal Clock Input................................................................ Count Timing for External Clock Input............................................................... Timing of CMF Setting........................................................................................ Timing of Timer Output ...................................................................................... Timing of Compare-Match Clear ........................................................................ Timing of Clearing by External Reset Input........................................................ Timing of OVF Setting ........................................................................................ Conflict between TCNT Write and Clear ............................................................ Conflict between TCNT Write and Increment..................................................... Conflict between TCOR Write and Compare-Match...........................................
263 263 264 264 265 265 266 269 270 271
Section 12 Programmable Pulse Generator (PPG) Figure 12.1 Block Diagram of PPG ........................................................................................ Figure 12.2 PPG Output Operation......................................................................................... Figure 12.3 Timing of Transfer and Output of NDR Contents (Example) ............................. Figure 12.4 Setup Procedure for Normal Pulse Output (Example)......................................... Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) ................................. Figure 12.6 Non-Overlapping Pulse Output ........................................................................... Figure 12.7 Non-Overlapping Operation and NDR Write Timing ......................................... Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example) ......................... Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) ............ Figure 12.10 Inverted Pulse Output (Example) ........................................................................ Figure 12.11 Pulse Output Triggered by Input Capture (Example) .......................................... Section 13 Watchdog Timer Figure 13.1 Block Diagram of WDT ...................................................................................... Figure 13.2 Example of WDT0 Watchdog Timer Operation.................................................. Figure 13.3 Writing to TCNT, TCSR, and RSTCSR (Example for WDT0)........................... Figure 13.4 Conflict between TCNT Write and Increment..................................................... Section 14 Serial Communication Interface (SCI) Figure 14.1 Block Diagram of SCI ......................................................................................... Figure 14.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) .............................................. Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode..................................... Figure 14.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) ......................................................................................... Figure 14.5 Sample SCI Initialization Flowchart.................................................................... Figure 14.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) ................................................ Figure 14.7 Sample Serial Transmission Flowchart ...............................................................
Rev. 3.00 Oct 04, 2005 page xxx of xl
276 284 285 286 287 288 289 290 291 293 294
296 300 302 302
306 330 332 333 334 335 336
Figure 14.8 Figure 14.9 Figure 14.9 Figure 14.10 Figure 14.11 Figure 14.12 Figure 14.13 Figure 14.13 Figure 14.14 Figure 14.15 Figure 14.16 Figure 14.17 Figure 14.18 Figure 14.19 Figure 14.20 Figure 14.21 Figure 14.22 Figure 14.23 Figure 14.24 Figure 14.25 Figure 14.26 Figure 14.27 Figure 14.28 Figure 14.29 Figure 14.30 Figure 14.31 Figure 14.32
Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) ....................................................................................................... Sample Serial Reception Data Flowchart (1)....................................................... Sample Serial Reception Data Flowchart (2)....................................................... Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)......................................... Sample Multiprocessor Serial Transmission Flowchart ...................................... Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ....................................................................... Sample Multiprocessor Serial Reception Flowchart (1) ...................................... Sample Multiprocessor Serial Reception Flowchart (2) ...................................... Data Format in Synchronous Communication (For LSB-First)........................... Sample SCI Initialization Flowchart.................................................................... Sample SCI Transmission Operation in Clocked Synchronous Mode ................ Sample Serial Transmission Flowchart ............................................................... Example of SCI Operation in Reception ............................................................. Sample Serial Reception Flowchart..................................................................... Sample Flowchart of Simultaneous Serial Transmit and Receive Operations..... Schematic Diagram of Smart Card Interface Pin Connections ............................ Normal Smart Card Interface Data Format.......................................................... Direct Convention (SDIR = SINV = O/E = 0)..................................................... Inverse Convention (SDIR = SINV = O/E = 1)................................................... Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate).................................................... Retransfer Operation in SCI Transmit Mode....................................................... TEND Flag Generation Timing in Transmission Operation................................ Example of Transmission Processing Flow ......................................................... Retransfer Operation in SCI Receive Mode ........................................................ Example of Reception Processing Flow .............................................................. Timing for Fixing Clock Output Level................................................................ Clock Halt and Restart Procedure........................................................................
337 339 340 342 343 344 345 346 347 348 350 351 352 353 355 356 357 358 358 360 362 362 363 364 365 366 367
Section 15 Controller Area Network (HCAN) Figure 15.1 HCAN Block Diagram......................................................................................... 372 Figure 15.2 Message Control Register Configuration............................................................. 396 Figure 15.3 Standard Format .................................................................................................. 396 Figure 15.4 Extended Format.................................................................................................. 396 Figure 15.5 Message Data Configuration ............................................................................... 398 Figure 15.6 Hardware Reset Flowchart................................................................................... 401 Figure 15.7 Software Reset Flowchart.................................................................................... 402 Figure 15.8 Detailed Description of One Bit .......................................................................... 403
Rev. 3.00 Oct 04, 2005 page xxxi of xl
Figure 15.9 Figure 15.10 Figure 15.11 Figure 15.12 Figure 15.13 Figure 15.14 Figure 15.15 Figure 15.16
Transmission Flowchart....................................................................................... Transmit Message Cancellation Flowchart.......................................................... Reception Flowchart............................................................................................ Unread Message Overwrite Flowchart ................................................................ HCAN Sleep Mode Flowchart............................................................................. HCAN Halt Mode Flowchart............................................................................... DTC Transfer Flowchart...................................................................................... High-Speed Interface Using PCA82C250 ...........................................................
406 408 409 412 413 415 417 418
Section 16 Synchronous Serial Communication Unit (SSU) Figure 16.1 Block Diagram of SSU ........................................................................................ Figure 16.2 Relationship of Clock Phase, Polarity, and Data ................................................. Figure 16.3 Relationship between Data I/O Pins and the Shift Register................................. Figure 16.4 Example of SSU Initialization ............................................................................. Figure 16.5 Example of Transmission Operation ................................................................... Figure 16.6 Example of Data Transmission Flowchart........................................................... Figure 16.7 Example of Reception Operation......................................................................... Figure 16.8 Example of Data Reception Flowchart ................................................................ Figure 16.9 Example of Simultaneous Transmission/Reception Flowchart ........................... Figure 16.10 Conflict Error Detection Timing (Before Transfer Start) .................................... Figure 16.11 Conflict Error Detection Timing (After Transfer End)........................................ Section 17 A/D Converter Figure 17.1 Block Diagram of A/D Converter........................................................................ Figure 17.2 A/D Conversion Timing ...................................................................................... Figure 17.3 External Trigger Input Timing............................................................................. Figure 17.4 A/D Conversion Accuracy Definitions................................................................ Figure 17.5 A/D Conversion Accuracy Definitions................................................................ Figure 17.6 Example of Analog Input Circuit......................................................................... Figure 17.7 Example of Analog Input Protection Circuit ....................................................... Figure 17.8 Analog Input Pin Equivalent Circuit.................................................................... Section 19 ROM Figure 19.1 Block Diagram of Flash Memory ....................................................................... Figure 19.2 Flash Memory State Transitions .......................................................................... Figure 19.3 Boot Mode ........................................................................................................... Figure 19.4 User Program Mode............................................................................................. Figure 19.5 Flash Memory Block Configuration .................................................................... Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode .................... Figure 19.7 Flowchart for Flash Memory Emulation in RAM ............................................... Figure 19.8 Example of RAM Overlap Operation ..................................................................
Rev. 3.00 Oct 04, 2005 page xxxii of xl
424 435 436 437 439 440 442 443 445 446 447
450 457 459 461 461 462 464 464
468 469 470 471 472 481 482 483
Figure 19.9 Program/Program-Verify Flowchart.................................................................... 485 Figure 19.10 Erase/Erase-Verify Flowchart.............................................................................. 487 Section 20 Clock Pulse Generator Figure 20.1 Block Diagram of Clock Pulse Generator ........................................................... Figure 20.2 Connection of Crystal Resonator (Example) ....................................................... Figure 20.3 Crystal Resonator Equivalent Circuit .................................................................. Figure 20.4 External Clock Input (Examples) ........................................................................ Figure 20.5 External Clock Input Timing ............................................................................... Figure 20.6 Note on Board Design of Oscillator Circuit ........................................................ Figure 20.7 External Circuitry Recommended for PLL Circuit.............................................. Section 21 Power-Down Modes Figure 21.1 Mode Transition Diagram.................................................................................... Figure 21.2 Medium-Speed Mode Transition and Clearance Timing..................................... Figure 21.3 Software Standby Mode Application Example.................................................... Figure 21.4 Timing of Transition to Hardware Standby Mode............................................... Figure 21.5 Timing of Recovery from Hardware Standby Mode ........................................... Section 23 Electrical Characteristics Figure 23.1 Output Load Circuit............................................................................................. Figure 23.2 System Clock Timing .......................................................................................... Figure 23.3 Oscillation Settling Timing.................................................................................. Figure 23.4 Reset Input Timing .............................................................................................. Figure 23.5 Interrupt Input Timing ......................................................................................... Figure 23.6 I/O Port Input/Output Timing .............................................................................. Figure 23.7 Realtime Input Port Data Input Timing ............................................................... Figure 23.8 TPU Input/Output Timing ................................................................................... Figure 23.9 TPU Clock Input Timing ..................................................................................... Figure 23.10 SCK Clock Input Timing..................................................................................... Figure 23.11 SCI Input/Output Timing (Clocked Synchronous Mode).................................... Figure 23.12 A/D Converter External Trigger Input Timing .................................................... Figure 23.13 HCAN Input/Output Timing................................................................................ Figure 23.14 PPG Output Timing ............................................................................................. Figure 23.15 8-Bit Timer Output Timing.................................................................................. Figure 23.16 8-Bit Timer Clock Input Timing.......................................................................... Figure 23.17 8-Bit Timer Reset Input Timing .......................................................................... Figure 23.18 SSU Timing (Master, CPHS = 1) ........................................................................ Figure 23.19 SSU Timing (Master, CPHS = 0) ........................................................................ Figure 23.20 SSU Timing (Slave, CPHS = 1)........................................................................... Figure 23.21 SSU Timing (Slave, CPHS = 0)...........................................................................
491 494 494 495 496 498 499
502 508 511 512 513
576 577 578 579 579 583 583 583 584 584 584 584 585 585 585 585 586 586 587 587 588
Rev. 3.00 Oct 04, 2005 page xxxiii of xl
Appendix Figure C.1
FP-100M Package Dimensions............................................................................ 594
Rev. 3.00 Oct 04, 2005 page xxxiv of xl
Tables
Section 2 CPU Table 2.1 Instruction Classification ....................................................................................... 27 Table 2.2 Operation Notation................................................................................................. 28 Table 2.3 Data Transfer Instructions...................................................................................... 29 Table 2.4 Arithmetic Operations Instructions (1) .................................................................. 30 Table 2.4 Arithmetic Operations Instructions (2) .................................................................. 31 Table 2.5 Logic Operations Instructions ................................................................................ 32 Table 2.6 Shift Instructions .................................................................................................... 33 Table 2.7 Bit Manipulation Instructions (1)........................................................................... 34 Table 2.7 Bit Manipulation Instructions (2)........................................................................... 35 Table 2.8 Branch Instructions ................................................................................................ 36 Table 2.9 System Control Instructions................................................................................... 37 Table 2.10 Block Data Transfer Instructions ........................................................................... 38 Table 2.11 Addressing Modes.................................................................................................. 40 Table 2.12 Absolute Address Access Ranges .......................................................................... 41 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection ........................................................................... 49 Section 4 Exception Handling Table 4.1 Exception Types and Priority................................................................................. Table 4.2 Exception Handling Vector Table.......................................................................... Table 4.3 Statuses of CCR and EXR after Trace Exception Handling .................................. Table 4.4 Statuses of CCR and EXR after Trap Instruction Exception Handling.................. Section 5 Interrupt Controller Table 5.1 Pin Configuration................................................................................................... Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................ Table 5.3 Interrupt Control Modes......................................................................................... Table 5.4 Interrupt Response Times ...................................................................................... Table 5.5 Number of States in Interrupt Handling Routine Execution Status........................ Section 8 Data Transfer Controller (DTC) Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................ Table 8.2 Register Information in Normal Mode................................................................... Table 8.3 Register Information in Repeat Mode.................................................................... Table 8.4 Register Information in Block Transfer Mode ....................................................... Table 8.5 DTC Execution Status............................................................................................
55 56 60 62
67 75 78 83 84
110 113 114 115 120
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Table 8.6
Number of States Required for Each Execution Status.......................................... 120
Section 9 I/O Ports Table 9.1 Port Functions ........................................................................................................ Table 9.2 P17 Pin Function.................................................................................................... Table 9.3 P16 Pin Function.................................................................................................... Table 9.4 P15 Pin Function.................................................................................................... Table 9.5 P14 Pin Function.................................................................................................... Table 9.6 P13 Pin Function.................................................................................................... Table 9.7 P12 Pin Function.................................................................................................... Table 9.8 P11 Pin Function.................................................................................................... Table 9.9 P10 Pin Function.................................................................................................... Table 9.10 P37 Pin Function.................................................................................................... Table 9.11 P36 Pin Function.................................................................................................... Table 9.12 P35 Pin Function.................................................................................................... Table 9.13 P34 Pin Function.................................................................................................... Table 9.14 P33 Pin Function.................................................................................................... Table 9.15 P32 Pin Function.................................................................................................... Table 9.16 P31 Pin Function.................................................................................................... Table 9.17 P30 Pin Function.................................................................................................... Table 9.18 P77 Pin Function.................................................................................................... Table 9.19 P76 Pin Function.................................................................................................... Table 9.20 P75 Pin Function.................................................................................................... Table 9.21 P74 Pin Function.................................................................................................... Table 9.22 P73 Pin Function.................................................................................................... Table 9.23 P72 Pin Function.................................................................................................... Table 9.24 P71 Pin Function.................................................................................................... Table 9.25 P70 Pin Function.................................................................................................... Table 9.26 PA3 Pin Function ................................................................................................... Table 9.27 PA2 Pin Function ................................................................................................... Table 9.28 PA1 Pin Function ................................................................................................... Table 9.29 PA0 Pin Function ................................................................................................... Table 9.30 PB7 Pin Function ................................................................................................... Table 9.31 PB6 Pin Function ................................................................................................... Table 9.32 PB5 Pin Function ................................................................................................... Table 9.33 PB4 Pin Function ................................................................................................... Table 9.34 PB3 Pin Function ................................................................................................... Table 9.35 PB2 Pin Function ................................................................................................... Table 9.36 PB1 Pin Function ................................................................................................... Table 9.37 PB0 Pin Function ................................................................................................... Table 9.38 PC7 Pin Function ...................................................................................................
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128 133 133 134 134 134 135 135 135 138 138 138 139 139 139 139 139 142 142 142 143 143 143 143 143 148 148 148 148 152 152 152 153 153 153 153 154 157
Table 9.39 Table 9.40 Table 9.41 Table 9.42 Table 9.43 Table 9.44 Table 9.45 Table 9.46 Table 9.47 Table 9.48 Table 9.49 Table 9.50 Table 9.51 Table 9.52 Table 9.53 Section 10 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Table 10.11 Table 10.12 Table 10.13 Table 10.14 Table 10.15 Table 10.16 Table 10.17 Table 10.18 Table 10.19 Table 10.20 Table 10.21 Table 10.22 Table 10.23 Table 10.24
PC6 Pin Function ................................................................................................... PC5 Pin Function ................................................................................................... PC4 Pin Function ................................................................................................... PC3 Pin Function ................................................................................................... PC2 Pin Function ................................................................................................... PC1 Pin Function ................................................................................................... PC0 Pin Function ................................................................................................... PF7 Pin Function.................................................................................................... PF6 Pin Function.................................................................................................... PF5 Pin Function.................................................................................................... PF4 Pin Function.................................................................................................... PF3 Pin Function.................................................................................................... PF2 Pin Function.................................................................................................... PF1 Pin Function.................................................................................................... PF0 Pin Function.................................................................................................... 16-Bit Timer Pulse Unit (TPU) TPU Functions ....................................................................................................... TPU Pins ................................................................................................................ CCLR2 to CCLR0 (Channels 0 and 3)................................................................... CCLR2 to CCLR0 (Channels 1, 2, 4, and 5).......................................................... TPSC2 to TPSC0 (Channel 0)................................................................................ TPSC2 to TPSC0 (Channel 1)................................................................................ TPSC2 to TPSC0 (Channel 2)................................................................................ TPSC2 to TPSC0 (Channel 3)................................................................................ TPSC2 to TPSC0 (Channel 4)................................................................................ TPSC2 to TPSC0 (Channel 5)................................................................................ MD3 to MD0.......................................................................................................... TIORH_0 (Channel 0) ........................................................................................... TIORL_0 (Channel 0)............................................................................................ TIOR_1 (Channel 1) .............................................................................................. TIOR_2 (Channel 2) .............................................................................................. TIORH_3 (Channel 3) ........................................................................................... TIORL_3 (Channel 3)............................................................................................ TIOR_4 (Channel 4) .............................................................................................. TIOR_5 (Channel 5) .............................................................................................. TIORH_0 (Channel 0) ........................................................................................... TIORL_0 (Channel 0)............................................................................................ TIOR_1 (Channel 1) .............................................................................................. TIOR_2 (Channel 2) .............................................................................................. TIORH_3 (Channel 3) ...........................................................................................
157 157 158 158 158 159 159 165 165 165 165 165 166 166 166
168 171 175 175 176 176 177 177 178 178 180 182 183 184 185 186 187 188 189 190 191 192 193 194
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Table 10.25 Table 10.26 Table 10.27 Table 10.28 Table 10.29 Table 10.30 Table 10.31 Table 10.32 Table 10.33 Table 10.34 Table 10.35 Table 10.36
TIORL_3 (Channel 3)............................................................................................ TIOR_4 (Channel 4) .............................................................................................. TIOR_5 (Channel 5) .............................................................................................. Register Combinations in Buffer Operation........................................................... Cascaded Combinations ......................................................................................... PWM Output Registers and Output Pins................................................................ Phase Counting Mode Clock Input Pins ................................................................ Up/Down-Count Conditions in Phase Counting Mode 1 ....................................... Up/Down-Count Conditions in Phase Counting Mode 2 ....................................... Up/Down-Count Conditions in Phase Counting Mode 3 ....................................... Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... TPU Interrupts .......................................................................................................
195 196 197 213 217 220 224 225 226 227 228 232
Section 11 8-Bit Timers Table 11.1 Pin Configuration................................................................................................... Table 11.2 8-Bit Timer Interrupt Sources ................................................................................ Table 11.3 Timer Output Priorities .......................................................................................... Table 11.4 Switching of Internal Clock and TCNT Operation ................................................
253 268 271 272
Section 12 Programmable Pulse Generator (PPG) Table 12.1 Pin Configuration................................................................................................... 277 Section 13 Watchdog Timer Table 13.1 WDT Interrupt Source ........................................................................................... 301 Section 14 Serial Communication Interface (SCI) Table 14.1 Pin Configuration................................................................................................... Table 14.2 The Relationships between The N Setting in BRR and Bit Rate B........................ Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ............................ Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ............................ Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ............................ Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372) ...................................................................................... Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (When S = 372)...................................................................................................... Table 14.10 Serial Transfer Formats (Asynchronous Mode)..................................................... Table 14.11 SSR Status Flags and Receive Data Handling .......................................................
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307 323 324 325 326 326 327 328 328 329 329 331 338
Table 14.12 SCI Interrupt Sources............................................................................................. 368 Table 14.13 SCI Interrupt Sources............................................................................................. 369 Section 15 Controller Area Network (HCAN) Table 15.1 HCAN Pins ............................................................................................................ 373 Table 15.2 Limits for the Settable Value ................................................................................. 403 Table 15.3 Setting Range for TSEG1 and TSEG2 in BCR ...................................................... 404 Table 15.4 HCAN Interrupt Sources........................................................................................ 416 Table 15.5 Interval Limitation between TXPR and TXPR or between TXPR and TXCR ...... 421 Section 16 Synchronous Serial Communication Unit (SSU) Table 16.1 Pin Configuration................................................................................................... 425 Table 16.2 Interrupt Souses ..................................................................................................... 448 Section 17 A/D Converter Table 17.1 Pin Configuration................................................................................................... 451 Table 17.2 Analog Input Channels and Corresponding ADDR Registers ............................... 452 Table 17.3 A/D Conversion Time (Single Mode).................................................................... 458 Table 17.4 A/D Conversion Time (Scan Mode) ...................................................................... 458 Table 17.5 A/D Converter Interrupt Source............................................................................. 459 Table 17.6 Analog Pin Specifications ...................................................................................... 464 Section 19 ROM Table 19.1 Differences between Boot Mode and User Program Mode.................................... Table 19.2 Pin Configuration................................................................................................... Table 19.3 Setting On-Board Programming Modes................................................................. Table 19.4 Boot Mode Operation............................................................................................. Table 19.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible .................................................................................................................. Table 19.6 Flash Memory Operating States............................................................................. Table 19.7 Registers Present in F-ZTAT Version but Absent in Masked ROM Version ........
469 473 477 479 479 489 490
Section 20 Clock Pulse Generator Table 20.1 Damping Resistance Value .................................................................................... 494 Table 20.2 Crystal Resonator Characteristics .......................................................................... 495 Table 20.3 External Clock Input Conditions............................................................................ 496 Section 21 Power-Down Modes Table 21.1 Low Power Consumption Mode Transition Conditions......................................... 502 Table 21.2 LSI Internal States in Each Mode .......................................................................... 503 Table 21.3 Oscillation Stabilization Time Settings.................................................................. 510
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Table 21.4
Pin State in Each Processing State ...................................................................... 514
Section 23 Electrical Characteristics Table 23.1 Absolute Maximum Ratings .................................................................................. Table 23.2 DC Characteristics ................................................................................................. Table 23.3 Permissible Output Currents .................................................................................. Table 23.4 Clock Timing ......................................................................................................... Table 23.5 Control Signal Timing............................................................................................ Table 23.6 Timing of On-Chip Peripheral Modules ................................................................ Table 23.7 Timing of SSU ....................................................................................................... Table 23.8 A/D Conversion Characteristics............................................................................. Table 23.9 Flash Memory Characteristics................................................................................
573 574 576 577 578 580 582 589 590
Rev. 3.00 Oct 04, 2005 page xl of xl
Section 1 Overview
Section 1 Overview
1.1 Overview
* High-speed H8S/2600 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 69 basic instructions * Various peripheral functions PC break controller Data transfer controller 16-bit timer-pulse unit (TPU) 8-bit timer (TMR) Programmable pulse generator (PPG) Watchdog timer Asynchronous or clocked synchronous serial communication interface (SCI) Controller area network (HCAN) Synchronous serial communication unit (SSU) 10-bit A/D converter Clock pulse generator * On-chip memory
ROM F-ZTAT Version Masked ROM Version Model HD64F2628 HD6432628 HD6432627 ROM 128 kbytes 128 kbytes 128 kbytes RAM 8 kbytes 8 kbytes 6 kbytes Remarks
* General I/O ports I/O pins: 59 Input-only pins: 17 * Supports various power-down states * Compact package
Package QFP-100 Package Code FP-100M Body Size 14.0 x 14.0 mm Pin Pitch 0.5 mm
Rev. 3.00 Oct 04, 2005 page 1 of 598 REJ09B0155-0300
Section 1 Overview
1.2
Internal Block Diagram
VCL VCC VCC VCC VSS VSS VSS
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port D
Internal address bus
PF7/ PF6 PF5 PF4 PF3/ADTRG/IRQ3 PF2 PF1/BUzz PF0/IRQ2
PC break controller (2 channels)
Port F
Peripheral data bus
Interrupt controller
DTC
Peripheral address bus
NMI
Port B
MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVSS STBY RES FWE/NC*
H8S/2600 CPU
Bus controller
Internal data bus
P L L
Clock pulse generator
PA3/SCK2 PA2/RxD2 PA1/TxD2 PA0
Port A
PB7/TIOCB5 PB6/TIOCA5 PB5/TIOCB4 PB4/TIOCA4 PB3/TIOCD3 PB2/TIOCC3 PB1/TIOCB3 PB0/TIOCA3 PC7/SCS1 PC6/SSCK1 PC5/SSI1 PC4/SSO1 PC3/SCS0 PC2/SSCK0 PC1/SSI0 PC0/SSO0 P37 P36 P35/IRQ5 P34 P33 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0
TMR x 4 channels SCI x 2 channels SSU x 2 channels
RAM
TPU
P77 P76 P75/TMO3 P74/TMO2 P73/TMO1 P72/TMO0 P71/TMCI23/TMRI23 P70/TMCIO1/TMRIO1
HCAN x 1 channel
Port 7
Port 3
Port C
ROM (Masked ROM, flash memory)
WDT x 1 channel
PPG
A/D converter
Port 9
Port 1
Port 4
P97/AN15 P96/AN14 P95/AN13 P94/AN12 P93/AN11 P92/AN10 P91/AN9 P90/AN8
P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0
HRxD HTxD Vref AVCC AVSS
Note: * The FWE pin is provided only in the flash memory version. The NC pin is provided only in the masked ROM version.
Figure 1.1 Internal Block Diagram
Rev. 3.00 Oct 04, 2005 page 2 of 598 REJ09B0155-0300
P47/ AN7 P46/ AN6 P45/ AN5 P44/ AN4 P43/ AN3 P42/ AN2 P41/ AN1 P40/ AN0
Section 1 Overview
1.3
Pin Arrangement
PF0/IRQ2 PF1 PF2 PF3/ADTRG/IRQ3 PF4 PF5 PF6 PF7/ PLLCAP FWE/NC* PLLVSS VSS EXTAL XTAL VCC NMI STBY VCL RES VSS MD2 MD1 MD0 P30/TxD0 P31/RxD0
P97/AN15 P96/AN14 P95/AN13 P94/AN12 P93/AN11 P92/AN10 P91/AN9 P90/AN8 AVSS Vref AVCC P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/TCLKA P13/PO11/TIOCD0/TCLKB P14/PO12/TIOCA1/IRQ0 P15/PO13/TIOCB1/TCLKC
75747372717069686766656463626160595857565554535251 76 50 77 49 78 48 79 47 80 46 81 45 82 44 83 43 84 42 85 41 86 40 87 39 FP-100M 88 38 (Top view) 89 37 90 36 91 35 92 34 93 33 94 32 95 31 96 30 97 29 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425
P16/PO14/TIOCA2/IRQ1 VCC P17/PO15/TIOCB2/TCLKD VSS HRxD HTxD P70/TMCI01/TMRI01 P71/TMCI23/TMRI23 P72/TMO0 P73/TMO1 P74/TMO2 P75/TMO3 P76 P77 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0/SSO0 PC1/SSI0 PC2/SSCK0
P32/SCK0/IRQ4 P33 P34 P35/IRQ5 P36 P37 PA3/SCK2 PA2/RxD2 PA1/TxD2 PA0 PB7/TIOCB5 PB6/TIOCA5 PB5/TIOCB4 PB4/TIOCA4 PB3/TIOCD3 PB2/TIOCC3 VSS PB1/TIOCB3 VCC PB0/TIOCA3 PC7/SCS1 PC6/SSCK1 PC5/SSI1 PC4/SSO1 PC3/SCS0
Note: * The FWE pin is provided only in the flash memory version. The NC pin is provided only in the masked ROM version.
Figure 1.2 Pin Arrangement
Rev. 3.00 Oct 04, 2005 page 3 of 598 REJ09B0155-0300
Section 1 Overview
1.4
Type Power Supply
Pin Functions
Symbol VCC Pin NO. 2 32 61 4 34 56 64 58 I/O Input Function Power supply pins. Connect all these pins to the system power supply. Ground pins. Connect all these pins to the system power supply (0 V).
VSS
Input
VCL
Output
External capacitance pin for internal power-down power supply. Connect this pin to VSS via a 0.1F capacitor (placed close to the pins). On-chip PLL oscillator ground pin. External capacitance pin for an on-chip PLL oscillator. For connection to a crystal resonator. For examples of crystal resonator connection and external clock input, see section 20, Clock Pulse Generator. For connection to a crystal resonator (An external clock can be supplied from the EXTAL pin). For examples of crystal resonator connection and external clock input, see section 20, Clock Pulse Generator. Supplies the system clock to external devices. Set the operating mode. Inputs at these pins should not be changed during operation. Reset input pin. When this pin is low, the chip is reset. When this pin is low, a transition is made to hardware standby mode. Pin for use by flash memory. This pin is only used in the flash memory version.
Clock
PLLVSS PLLCAP XTAL
65 67 62
Input Output Input
EXTAL
63
Input
Operating mode control System control MD2 MD1 MD0
68 55 54 53 57 59 66
Output Input
Input Input Input
Rev. 3.00 Oct 04, 2005 page 4 of 598 REJ09B0155-0300
YBTS
FWE
SER
Section 1 Overview Type Interrupts Symbol NMI Pin NO. 60 47 50 72 75 1 99 97 98 100 3 95 96 97 98 99 100 1 3 31 33 35 36 37 38 39 40 3 1 100 99 98 97 96 95 I/O Input Input Function Nonmaskable interrupt pin. If this pin is not used, it should be fixed high. These pins request a maskable interrupt.
16-bit timer- TCLKA pulse unit TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Programmable pulse generator (PPG) PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8
0QRI 1QRI 2QRI 3QRI 4QRI 5QRI
Input
These pins input an external clock.
Input/ Output
TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins.
Input/ Output Input/ Output Input/ Output
TGRA_1 to TGRB_1 input capture input/output compare output/PWM output pins. TGRA_2 to TGRB_2 input capture input/output compare output/PWM output pins. TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins.
Input/ Output Input/ Output Output
TGRA_4 to TGRB_4 input capture input/output compare output/PWM output pins. TGRA_5 to TGRB_5 input capture input/output compare output/PWM output pins. Pulse output pins.
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Section 1 Overview Type 8-bit timer (TMR) Symbol TMO3 TMO2 TMO1 TMO0 TMCI23 TMCI01 8-bit timer (TMR) Serial communication Interface (SCI)/ smart card interface HCAN TMRI23 TMRI01 TxD2 TxD0 RxD2 RxD0 SCK2 SCK0 HTxD HRxD Synchronous serial communication unit (SSU) SSO1 SSO0 SSI1 SSI0 SSCK1 SSCK0 Pin NO. 12 11 10 9 8 7 8 7 42 52 43 51 44 50 6 5 27 23 28 24 29 25 30 26 I/O Output Function Compare-match output pins.
Input Input Output Input Input/ Output Output Input Input/ Output Input/ Output Input/ Output Input/ Output
Input pins of external clocks input to the counter. Counter reset input pins. Data output pins. Data input pins. Clock input/output pins. CAN bus transmission pin. CAN bus reception pin. Data input/output pins. Data input/output pins. Clock input/output pins. Chip select input/output pins.
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0SCS 1SCS
Section 1 Overview Type A/D converter Symbol AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Pin NO. 76 77 78 79 80 81 82 83 87 88 89 90 91 92 93 94 72 86 I/O Input Function Analog input pins.
Input Input
Pin for input of an external trigger to start A/D conversion. Power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V). The ground pin for the A/D converter. Connect this pin to the system power supply (0 V). The reference voltage input pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V). Eight input/output pins.
I/O ports
GRTDA
AVCC AVSS Vref P17 P16 P15 P14 P13 P12 P11 P10
84 85
Input Input
3 1 100 99 98 97 96 95
Input/ Output
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Section 1 Overview Type I/O ports Symbol P37 P36 P35 P34 P33 P32 P31 P30 P47 P46 P45 P44 P43 P42 P41 P40 P77 P76 P75 P74 P73 P72 P71 P70 P97 P96 P95 P94 P93 P92 P91 P90 PA3 PA2 PA1 PA0 Pin NO. 45 46 47 48 49 50 51 52 87 88 89 90 91 92 93 94 14 13 12 11 10 9 8 7 76 77 78 79 80 81 82 83 44 43 42 41 I/O Input/ Output Function Eight input/output pins.
Input
Eight input pins.
Input/ Output
Eight input/output pins.
Input
Eight input pins.
Input/ Output
Four input/output pins.
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Section 1 Overview Type I/O ports Symbol PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Pin NO. 40 39 38 37 36 35 33 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 68 69 70 71 72 73 74 75 I/O Input/ Output Function Eight input/output pins.
Input/ Output
Eight input/output pins.
Input/ Output
Eight input/output pins.
Input/ Output
Eight input/output pins.
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Section 1 Overview
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Section 2 CPU
Section 2 CPU
The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1
Features
* Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H CPUs object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 3 states 16 / 8-bit register-register divide: 12 states
CPUS260A_000020020300
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Section 2 CPU
16 x 16-bit register-register multiply: 4 states 32 / 16-bit register-register divide: 20 states * Two CPU operating modes Normal mode* Advanced mode * Power-down state Transition to power-down state by the SLEEP instruction CPU clock speed selection Note: * Normal mode is not available in this LSI. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. * Register configuration The MAC register is supported by the H8S/2600 CPU only. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600 CPU only. * The number of execution states of the MULXU and MULXS instructions;
Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21
In addition, there are differences in address space, CCR and EXR register functions, and powerdown modes, etc., depending on the model.
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Section 2 CPU
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements: * More general registers and control registers Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.3 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements: * More control registers One 8-bit and two 32-bit control registers have been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast.
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Section 2 CPU
2.2
CPU Operating Modes
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU. * Address Space Linear access to a 64-kbyte maximum address space is provided. * Extended Registers (En) The extended registers (E7 to E0) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table structure in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the area from H'0000 to H'00FF. Note that the first part of this range is also used for the exception vector table. * Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: Normal mode is not available in this LSI.
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Section 2 CPU
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Exception vector 1 Exception vector 2 Exception vector 3 Exception vector 4 Exception vector 5 Exception vector 6 Exception vector table
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC (16 bits)
SP (SP *
2
EXR*1 Reserved*1*3 ) CCR CCR*3 PC (16 bits)
(a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning.
(b) Exception Handling
Figure 2.2 Stack Structure in Normal Mode 2.2.2 Advanced Mode
* Address Space Linear access to a 16-Mbyte maximum address space is provided. * Extended Registers (En) The extended registers (E7 to E0) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers.
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Section 2 CPU
* Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling.
H'00000000 Reserved Exception vector 1 H'00000003 H'00000004 Reserved Exception vector 2 H'00000007 H'00000008 Reserved Exception vector table Exception vector 3 H'0000000B H'0000000C Reserved Exception vector 4 H'00000010 Reserved Exception vector 5
Figure 2.3 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also used for the exception vector table.
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Section 2 CPU
* Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling.
SP SP Reserved PC (24 bits) (SP *2 )
EXR*1 Reserved*1*3 CCR PC (24 bits)
(a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning.
(b) Exception Handling
Figure 2.4 Stack Structure in Advanced Mode
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Section 2 CPU
2.3
Address Space
Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
H'0000 64 kbytes H'FFFF 16 Mbytes Program area H'00000000
H'00FFFFFF
Data area
Cannot be used for this LSI
H'FFFFFFFF (a) Normal Mode (b) Advanced Mode
Figure 2.5 Memory Map
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Section 2 CPU
2.4
Registers
The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC).
General Registers (Rn) and Extended Registers (En)
15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Control Registers (CR)
23 PC 0
EXR T
76543210 - - - - I2 I1 I0
76543210
CCR I UI H U N Z V C 63 MAC 31 (Sign extension) MACL 0 41 MACH 32
Legend:
SP: PC: EXR: T: I2 to I0: CCR: I: UI: Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit H: U: N: Z: V: C: MAC: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register
Figure 2.6 CPU Registers
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Section 2 CPU
2.4.1
General Registers
The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER7 to ER0). The ER registers divide into 16-bit general registers designated by the letters E (E7 to E0) and R (R7 to R0). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E7 to E0) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R7H to R0H) and RL (R7L to R0L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers. The usage of each register can be selected independently. General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack.
* Address registers * 32-bit registers * 16-bit registers * 8-bit registers
E registers (extended registers) (E7 to E0) ER registers (ER7 to ER0) R registers (R7 to R0) RL registers (R7L to R0L) RH registers (R7H to R0H)
Figure 2.7 Usage of General Registers
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Section 2 CPU
Free area SP (ER7)
Stack area
Figure 2.8 Stack 2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored (When an instruction is fetched, the least significant PC bit is regarded as 0). 2.4.3 Extended Control Register (EXR)
EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions, except for the STC instruction, are executed, all interrupts including NMI will be masked for three states after execution is completed.
Bit 7 Bit Name T Initial Value 0 R/W R/W Description Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 2 1 0
I2 I1 I0
All 1 1 1 1
R/W R/W R/W
Reserved These bits are always read as 1. These bits designate the interrupt mask level (7 to 0). For details, refer to section 5, Interrupt Controller.
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Section 2 CPU
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. 6 UI undefined R/W User Bit or Interrupt Mask Bit Can be read or written by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit cannot be used as an interrupt mask bit in this LSI. 5 H undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U undefined R/W User Bit Can be read or written by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit.
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Section 2 CPU Bit 2 Bit Name Z Initial Value undefined R/W R/W Description Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 C undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
2.4.5
Multiply-Accumulate Register (MAC)
This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.6 Initial Values of CPU Registers
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset.
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Section 2 CPU
2.5
Data Formats
The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats
Figure 2.9 shows the data formats in general registers.
Data Type
1-bit data
Register Number
RnH
Data Format
7 0 Don't care 76 54 32 10
7 1-bit data RnL Don't care
0
76 54 32 10
7 4-bit BCD data RnH Upper
43 Lower
0 Don't care
7 4-bit BCD data RnL Don't care Upper
43 Lower
0
7 Byte data RnH MSB
0 Don't care LSB 7 0 LSB
Byte data
RnL
Don't care MSB
Figure 2.9 General Register Data Formats (1)
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Section 2 CPU
Data Type Word data
Register Number Rn
Data Format
15
0
MSB
LSB
Word data
15
En
0
MSB
LSB
Longword data
31
ERn
16 15 0
MSB
En
Rn
LSB
Legend:
ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit
Figure 2.9 General Register Data Formats (2)
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Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 is used as an address register to access the stack, the operand size should be word or longword.
Data Type Address
7 1-bit data Address L 7 6 5 4 3 2 1
Data Format
0 0
Byte data
Address L
MSB
LSB
Word data
Address 2M Address 2M+1
MSB LSB
Longword data
Address 2N Address 2N+1 Address 2N+2 Address 2N+3
MSB
LSB
Figure 2.10 Memory Data Formats
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Section 2 CPU
2.6
Instruction Set
The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1. Table 2.1
Function Data transfer
Instruction Classification
Instructions MOV POP*1, PUSH*1 LDM, STM MOVFPE*3, MOVTPE*3 Size B/W/L W/L L B B/W/L B B/W/L L B/W W/L B B/W/L B/W/L B 4 8 14 5 9 1 23 Types 5
Arithmetic operations
ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*4 MAC, LDMAC, STMAC, CLRMAC
Logic operations Shift Bit manipulation Branch System control Block data transfer Notes: B: W: L: 1.
AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc*2, JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV
Total: 69 Byte Word Longword POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+,Rn and MOV.W Rn,@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+,ERn and MOV.L ERn,@-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 3.00 Oct 04, 2005 page 27 of 598 REJ09B0155-0300
Section 2 CPU
2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2
Symbol Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x /
Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length
:8/:16/:24/:32 Note: *
General registers include 8-bit registers (R7H to R0H, R7L to R0L), 16-bit registers (R7 to R0, E7 to E0), and 32-bit registers (ER7 to ER0).
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Section 2 CPU
Table 2.3
Instruction MOV
Data Transfer Instructions
Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack.
MOVFPE MOVTPE POP
B B W/L
PUSH
W/L
LDM STM Note: *
L L
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.4
Instruction ADD SUB
Arithmetic Operations Instructions (1)
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction). Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2 (Byte operands can be incremented or decremented by 1 only). Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU
B
B/W/L
L B
B/W
MULXS
B/W
DIVXU
B/W
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.4
Instruction DIVXS
Arithmetic Operations Instructions (2)
Size*1 B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1. (EAs) x (EAd) + MAC MAC Performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. The following operations can be performed: 16 bits x 16 bits + 32 bits 32 bits, saturating 16 bits x 16 bits + 42 bits 42 bits, non-saturating 0 MAC Clears the multiply-accumulate register to zero. Rs MAC, MAC Rd Transfers data between a general register and a multiply-accumulate register.
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
TAS*2 MAC
B
CLRMAC LDMAC STMAC Note:
L
1. Refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
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Section 2 CPU
Table 2.5
Instruction AND
Logic Operations Instructions
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
(Rd) (Rd)
Takes the one's complement (logical complement) of general register contents.
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.6
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: *
Shift Instructions
Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shifts are possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shifts are possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotations are possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotations are possible.
B/W/L
B/W/L
B/W/L
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.7
Instruction BSET
Bit Manipulation Instructions (1)
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BCLR
B
BNOT
B
( of ) ( of )
Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BTST
B
( of ) Z
Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BAND
B
C ( of ) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C [( of )] C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C [( of )] C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BIAND
B
BOR
B
BIOR
B
Note:
*
Refers to the operand size. B: Byte
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Section 2 CPU
Table 2.7
Instruction BXOR
Bit Manipulation Instructions (2)
Size* B Function C ( of ) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C [( of )] C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag.
BIXOR
B
BLD
B
BILD
B
( of ) C
Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data.
BST
B
C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand.
BIST
B
C ( of )
Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
Note:
*
Refers to the operand size. B: Byte
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Section 2 CPU
Table 2.8
Instruction Bcc
Branch Instructions
Size Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1
JMP BSR JSR RTS

Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine
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Section 2 CPU
Table 2.9
Instruction TRAPA RTE SLEEP LDC
System Control Instructions
Size* B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves general register or memory contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically XORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter.
STC
B/W
ANDC ORC XORC NOP Note: *
B B B
Refers to the operand size. B: Byte W: Word
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Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction EEPMOV.B Size Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed.
EEPMOV.W
2.6.2
Basic Instruction Formats
The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branching condition of Bcc instructions.
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Section 2 CPU
(1) Operation field only op NOP, RTS, etc.
(2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension op EA(disp) rn rm MOV.B @(d:16, Rn), Rm, etc.
(4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:16, etc.
Figure 2.11 Instruction Formats (Examples)
2.7
Addressing Modes and Effective Address Calculation
The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
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Section 2 CPU
Table 2.11 Addressing Modes
No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
2.7.1
Register DirectRn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect@ERn
The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added.
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Section 2 CPU
2.7.4
Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn
Register indirect with post-increment@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. Register indirect with pre-decrement@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges
Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode* H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF
Note: Normal mode is not available in this LSI.
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Section 2 CPU
2.7.6
Immediate#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 2.7.8 Memory Indirect@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address (For further information, see section 2.5.2, Memory Data Formats). Note: Normal mode is not available in this LSI.
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Section 2 CPU
Specified by @aa:8
Branch address
Specified by @aa:8
Reserved Branch address
(a) Normal Mode*
Note: * Normal mode is not available in this LSI.
(a) Advanced Mode
Figure 2.12 Branch Address Specification in Memory Indirect Mode 2.7.9 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI.
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Section 2 CPU
Table 2.13 Effective Address Calculation (1)
No 1
Addressing Mode and Instruction Format
Register direct(Rn)
Effective Address Calculation
Effective Address (EA)
Operand is general register contents.
op 2
rm
rn 31
General register contents
Register indirect(@ERn)
0
31
24 23
0
Don't care
op 3
r
Register indirect with displacement @(d:16,ERn) or @(d:32,ERn)
31
General register contents
0 31 24 23 0
op
r
disp 31
Sign extension
Don't care 0 disp
4
Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+
31
General register contents
0
31
24 23
0
Don't care
op
r 31
1, 2, or 4
*Register indirect with pre-decrement @-ERn
0
General register contents
31
24 23
0
Don't care op r
Operand Size Byte Word Longword 1, 2, or 4
Offset 1 2 4
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Section 2 CPU
Table 2.13 Effective Address Calculation (2)
No 5
Addressing Mode and Instruction Format
Absolute address
Effective Address Calculation
Effective Address (EA)
@aa:8 op abs
31
24 23 H'FFFF
87
0
Don't care
@aa:16 op abs
31
24 23
16 15
0
Don't care Sign extension
@aa:24 op abs
31
24 23
0
Don't care
@aa:32 op abs 31 24 23 0
Don't care
6
Immediate
#xx:8/#xx:16/#xx:32 op IMM
Operand is immediate data.
7
Program-counter relative @(d:8,PC)/@(d:16,PC)
23
PC contents
0
op
disp
23
Sign extension
0 disp 31 24 23 0
Don't care
8
Memory indirect @@aa:8 * Normal mode*
31 op abs H'000000 15
87 abs
0
0
Memory contents
31
24 23
16 15 H'00
0
Don't care
* Advanced mode
31 op abs 31
Memory contents
87 H'000000 abs
0 31 24 23 Don't care 0
0
Note: * Normal mode is not available in this LSI.
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Section 2 CPU
2.8
Processing States
The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. * Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. input goes low, all current processing stops and the CPU enters the reset state. When the All interrupts are masked in the reset state. Reset exception handling starts when the signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program Execution State In this state, the CPU executes program instructions in sequence. * Bus-Released State The bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further details, refer to section 21, Power-Down Modes.
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Section 2 CPU
Reset state*
R
ES
=H
igh
, igh = H ow BY = L ST ES R
Exception handling state
In reqterru ue pt st
Bus-released state
Request for exception handling
End of exception handling
s Bu est u req
Bus request
End of bus request
s bu of t nd ques Ee r
SLEEP instruction Program halt state
Program execution state
Notes: From any state, a transition to hardware standby mode occurs when STBY goes low. * From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows.
Figure 2.13 State Transitions
2.9
2.9.1
Usage Note
Notes on Using the Bit Operation Instruction
Instructions BSET, BCLR, BNOT, BST, and BIST read data in byte units, and write data in byte units after bit operation. Therefore, attention must be paid when these instructions are used for ports or registers including write-only bits. Instruction BCLR can be used to clear the flag in the internal I/O register to 0. If it is obvious that the flag has been set to 1 by the interrupt processing routine, it is unnecessary to read the flag beforehand.
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Section 2 CPU
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1 Operating Mode Selection
This LSI supports only operating mode 7, that is, the advanced single-chip mode. The operating mode is determined by the setting of the mode pins (MD2 to MD0). Only mode 7 can be used in this LSI. Therefore, all mode pins must be fixed high, as shown in table 3.1. Do not change the mode pin settings during operation. Table 3.1 MCU Operating Mode Selection
CPU Operating Mode Description Advanced mode Single-chip mode External Data Bus On-Chip ROM Enabled Initial Width Max. Width
MCU Operating Mode MD2 MD1 MD0 7 1 1 1
3.2
Register Descriptions
The following registers are related to the operating mode. * Mode control register (MDCR) * System control register (SYSCR)
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Section 3 MCU Operating Modes
3.2.1
Bit 7 6 to 3 2 1 0
Mode Control Register (MDCR)
Bit Name Initial Value 1 All 0 R/W R/W Descriptions Reserved Only 1 should be written to this bit. Reserved These bits are always read as 0 and cannot be modified. MDS2 MDS1 MDS0 R R R Mode select 2 to 0 These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are readonly bits and they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset.
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Section 3 MCU Operating Modes
3.2.2
System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and enables or disables on-chip RAM.
Bit 7 Bit Name MACS Initial Value 0 R/W R/W Descriptions MAC Saturation Selects either saturating or non-saturating calculation for the MAC instruction. 0: Non-saturating calculation for the MAC instruction 1: Saturating calculation for the MAC instruction Reserved This bit is always read as 0 and cannot be modified. These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Setting prohibited 10: Interrupt control mode 2 11: Setting prohibited NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input Reserved These bits are always read as 0 and cannot be modified. RAM Enable Enables or disables on-chip RAM. The RAME bit is initialized when the reset status is released. 0: On-chip RAM is disabled 1: On-chip RAM is enabled
6 5 4
INTM1 INTM0
0 0 0
R/W R/W
3
NMIEG
0
R/W
2, 1
All 0
0
RAME
1
R/W
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Section 3 MCU Operating Modes
3.3
Pin Functions in Each Operating Mode
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, however external addresses cannot be accessed. All I/O ports are available for use as input-output ports.
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Section 3 MCU Operating Modes
3.4
Address Map
Figure 3.1 shows the address map in each operating mode.
H8S/2628 ROM: 128 kbytes, RAM: 8 kbytes Mode 7 Advanced single-chip mode H'000000 H'000000 H8S/2627 ROM: 128 kbytes, RAM: 6 kbytes Mode 7 Advanced single-chip mode
On-chip ROM (F-ZTAT/masked ROM)
On-chip ROM (Masked ROM)
H'01FFFF
H'01FFFF
H'FFD000 On-chip RAM H'FFEFBF H'FFD800 On-chip RAM H'FFEFBF
H'FFF800 Internal I/O registers H'FFFF3F
H'FFF800 Internal I/O registers H'FFFF3F
H'FFFF60 Internal I/O registers H'FFFFBF H'FFFFC0 On-chip RAM H'FFFFFF
H'FFFF60 Internal I/O registers H'FFFFBF H'FFFFC0 On-chip RAM H'FFFFFF
Figure 3.1 Address Map
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Section 3 MCU Operating Modes
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Section 4 Exception Handling
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As shown in table 4.1, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, refer to section 5, Interrupt Controller. Table 4.1
Priority High
Exception Types and Priority
Exception Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the pin, or when the watchdog timer overflows. The CPU enters the reset state when the pin is low. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit in EXR is set to 1. Starts when a direction transition occurs as the result of SLEEP instruction execution. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued.*2 Started by execution of a trap instruction (TRAPA).
Trace*1 Direct transition Interrupt Low Trap instruction *3
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state.
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, refer to section 3, MCU Operating Modes.
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Section 4 Exception Handling
Table 4.2
Exception Handling Vector Table
Vector Address*1
Exception Source Power-on reset Manual reset *2 Reserved for system use
Vector Number 0 1 2 3 4
Normal Mode H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0019 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'00FE to H'00FF
Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H''0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'01FC to H'01FF
5 *2 6 Interrupt (direct transitions) Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) Reserved for system use 7 8 9 10 11 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved for system use Internal interrupt*3 16 17 18 19 20 21 22 23 24 127
Trace
Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table.
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Section 4 Exception Handling
4.3
Reset
A reset has the highest exception priority. When the pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the pin low for at least 20 ms at power-up. To reset the chip during operation, hold the pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details, see section 13, Watchdog Timer. The interrupt control mode is 0 immediately after reset. 4.3.1 Reset Exception Handling
pin goes high after being held low for the necessary period, this LSI starts reset When the exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, the T bit in EXR is cleared to 0, and the I bit in EXR and CCR is set to 1. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.1 and 4.2 show examples of the reset sequence.
SER
SER
SER SER
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Section 4 Exception Handling
Vector fetch
Fetch of first Internal processing program instruction
RES
Internal address bus
(1)
(3)
(5)
Internal read signal
Internal write signal Internal data bus
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction
Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)
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Section 4 Exception Handling
Vector fetch
Internal processing
Fetch of first program instruction
*
*
*
RES
Address bus
(1)
(3)
(5)
RD
HWR, LWR
High
D15 to D0
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Three program wait states are inserted.
Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled: Not Available in this LSI) 4.3.2 Interrupts after Reset
If an interrupt is accepted immediately after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset exception handling is executed. Since the first instruction of a program is always executed immediately after the reset, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP).
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Section 4 Exception Handling
4.3.3
State of On-Chip Peripheral Modules after Reset Release
After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively, and all modules except the DTC enter module stop mode. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when the module stop mode is cancelled.
4.4
Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt mask bit in CCR. Table 4.3 shows the states of CCR and EXR after execution of trace exception handling. Trace mode is cancelled by clearing the T bit in EXR to 0 with the trace exception handling. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.3 Statuses of CCR and EXR after Trace Exception Handling
CCR I UI I2 to I0 EXR T
Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution
Trace exception handling cannot be used. 1 -- -- 0
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Section 4 Exception Handling
4.5
Interrupts
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved to the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution begins from that address.
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Section 4 Exception Handling
4.6
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved to the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the statuses of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Statuses of CCR and EXR after Trap Instruction Exception Handling
CCR I 1 1 UI -- -- I2 to I0 -- -- EXR T -- 0
Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution
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Section 4 Exception Handling
4.7
Stack Status after Exception Handling
Figures 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling.
(a) Normal Modes*2
SP
EXR Reserved*1
SP
CCR CCR*1 PC (16 bits)
CCR CCR*1 PC (16 bits)
Interrupt control mode 0
Interrupt control mode 2
(b) Advanced Modes
SP
EXR Reserved*1
SP
CCR PC (24 bits)
CCR PC (24 bits)
Interrupt control mode 0 Notes: 1. Ignored on return. 2. Normal modes are not available in this LSI.
Interrupt control mode 2
Figure 4.3 Stack Status after Exception Handling
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Section 4 Exception Handling
4.8
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers:
PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of what happens when the SP value is odd.
Address
CCR SP PC
SP
R1L
H'FFFEFA H'FFFEFB
PC
H'FFFEFC H'FFFEFD H'FFFEFE
SP
H'FFFEFF
SP set to H'FFFEFF
TRAP instruction executed Data saved above SP
MOV.B R1L, @-ER7 instruction executed Contents of CCR lost
Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 4.4 Operation when SP Value Is Odd
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1 Features
* Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Seven external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ5 to IRQ0. * DTC control The DTC can be activated by an interrupt request.
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Section 5 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1.
INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I Interrupt request Vector number
CPU
Internal interrupt request SWDTEND to SSERT_i1
CCR I2 to I0 EXR
IPR Interrupt controller Legend: ISCR: IER: ISR: IPR: SYSCR:
IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register
Figure 5.1 Block Diagram of Interrupt Controller
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Section 5 Interrupt Controller
5.2
Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller. Table 5.1
Name NMI
Pin Configuration
I/O Input Input Input Input Input Input Input Function Nonmaskable external interrupt Rising or falling edge can be selected. Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected.
5.3
The interrupt controller has the following registers. For the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR). * * * * * * * * * * * * * * * * * System control register (SYSCR) IRQ sense control register H (ISCRH) IRQ sense control register L (ISCRL) IRQ enable register (IER) IRQ status register (ISR) Interrupt priority register A (IPRA) Interrupt priority register B (IPRB) Interrupt priority register C (IPRC) Interrupt priority register D (IPRD) Interrupt priority register E (IPRE) Interrupt priority register F (IPRF) Interrupt priority register G (IPRG) Interrupt priority register H (IPRH) Interrupt priority register I (IPRI) Interrupt priority register J (IPRJ) Interrupt priority register K (IPRK) Interrupt priority register L (IPRL)
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5QRI 4QRI 3QRI 2QRI 1QRI 0QRI
Register Descriptions
Section 5 Interrupt Controller
* Interrupt priority register M (IPRM) 5.3.1 Interrupt Priority Registers A to M (IPRA to IPRM)
The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a value in the range from H'7 to H'0 in the 3-bit groups of bits 2 to 0 and 6 to 4 sets the priority of the corresponding interrupt.
Bit 7 6 5 4 Bit Name Initial Value 0 1 1 1 R/W Description Reserved These bits are always read as 0. IPR6 IPR5 IPR4 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 3 2 1 0
IPR2 IPR1 IPR0
0 1 1 1
R/W R/W R/W
Reserved These bits are always read as 0. Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest)
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Section 5 Interrupt Controller
5.3.2
IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that controls the enabling and disabling of interrupt requests IRQ5 to IRQ0.
Bit 7, 6 5 Bit Name Initial Value All 0 0 R/W R/W R/W Description Reserved Only 0 should be written to these bits. IRQ5E IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. 4 IRQ4E 0 R/W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. 3 IRQ3E 0 R/W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. 2 IRQ2E 0 R/W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. 1 IRQ1E 0 R/W IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. 0 IRQ0E 0 R/W IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1.
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Section 5 Interrupt Controller
5.3.3
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
The ISCR registers are 16-bit readable/writable registers that select the source that generates an to . interrupt request at pins *
Bit 15 to 12 11 10
ISCRH
Bit Name Initial Value All 0 0 0 R/W R/W R/W R/W Description Reserved Only 0 should be written to these bits. IRQ5SCB IRQ5SCA IRQ5 Sense Control B IRQ5 Sense Control A
5QRI
10: Interrupt request generated at rising edge of input 11: Interrupt request generated at both falling and rising edges of input 9 8 IRQ4SCB IRQ4SCA 0 0 R/W R/W IRQ4 Sense Control B IRQ4 Sense Control A
4QRI 5QRI 5QRI
00: Interrupt request generated at level low
4QRI
01: Interrupt request generated at falling edge of input 10: Interrupt request generated at rising edge of input 11: Interrupt request generated at both falling and rising edges of input
4QRI 4QRI
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5QRI
0QRI
5QRI
00: Interrupt request generated at level low
input
01: Interrupt request generated at falling edge of input
input
Section 5 Interrupt Controller
*
Bit 7 6
ISCRL
Bit Name IRQ3SCB IRQ3SCA Initial Value 0 0 R/W R/W R/W Description IRQ3 Sense Control B IRQ3 Sense Control A
3QRI 2QRI 1QRI
00: Interrupt request generated at level low
3QRI
input
01: Interrupt request generated at falling edge of input 10: Interrupt request generated at rising edge of input 11: Interrupt request generated at both falling and rising edges of input 5 4 IRQ2SCB IRQ2SCA 0 0 R/W R/W IRQ2 Sense Control B IRQ2 Sense Control A 00: Interrupt request generated at level low
2QRI 3QRI 3QRI 2QRI 1QRI
input
01: Interrupt request generated at falling edge of input 10: Interrupt request generated at rising edge of input 11: Interrupt request generated at both falling and rising edges of input 3 2 IRQ1SCB IRQ1SCA 0 0 R/W R/W IRQ1 Sense Control B IRQ1 Sense Control A 00: Interrupt request generated at level low
1QRI 2QRI 1QRI
input
01: Interrupt request generated at falling edge of input 10: Interrupt request generated at rising edge of input 11: Interrupt request generated at both falling and rising edges of input
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Section 5 Interrupt Controller Bit 1 0 Bit Name IRQ0SCB IRQ0SCA Initial Value 0 0 R/W R/W R/W Description IRQ0 Sense Control B IRQ0 Sense Control A
0QRI
00: Interrupt request generated at level low
0QRI
input
01: Interrupt request generated at falling edge of input 10: Interrupt request generated at rising edge of input 11: Interrupt request generated at both falling and rising edges of input
0QRI 0QRI
5.3.4
IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt requests.
Bit 7, 6 5 4 3 2 1 0 Bit Name Initial Value All 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved Only 0 should be written to these bits. IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F [Setting condition] * When the interrupt source selected by the ISCR registers occurs Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set and input is high When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0
nQRI
[Clearing conditions] * *
*
*
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Section 5 Interrupt Controller
5.4
5.4.1
Interrupt Sources
External Interrupts
There are seven external interrupts: NMI and IRQ5 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin.
5QRI
IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins to . Interrupts IRQ5 to IRQ0 have the following features:
0QRI
* Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling to . edge, rising edge, or both edges, at pins * Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER. * The interrupt priority level can be set with IPR. * The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. The detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0; and use the pin as an I/O pin for another function. A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5.2.
IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n = 5 to 0 S R Q IRQn interrupt request
0QRI 5QRI
Figure 5.2 Block Diagram of Interrupts IRQ5 to IRQ0
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Section 5 Interrupt Controller
5.4.2
Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR. * The DTC can be activated by a TPU, SCI, or other interrupt request. * When the DTC is activated by an interrupt request, it is not affected by the interrupt control mode or CPU interrupt mask bit.
5.5
Interrupt Exception Handling Vector Table
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed.
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Section 5 Interrupt Controller
Table 5.2
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector Address*
Interrupt Source External pin
Origin of Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5
Vector Number 7 16 17 18 19 20 21 22 23 24 25 27 28 32 33 34 35 36 40 41 42 43 44 45 46 47
Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'006C H'0070 H'0080 H'0084 H'0088 H'008C H'0090 H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC
IPR
Priority High
IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB6 to IPRB4
IPRB2 to IPRB0
--
Reserved for system use SWDTEND WOVI0 PC break ADI TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0
DTC Watchdog timer 0 PC break control A/D TPU channel 0
IPRC2 to IPRC0 IPRD6 to IPRD4 IPRE6 to IPRE4 IPRE2 to IPRE0 IPRF6 to IPRF4
TPU channel 1
TGIA_1 TGIB_1 TCIV_1 TCIU_1
IPRF2 to IPRF0
TPU channel 2
TGIA_2 TGIB_2 TCIV_2 TCIU_2
IPRG6 to IPRG4
Low
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Section 5 Interrupt Controller Vector Address* Interrupt Source TPU channel 3 Origin of Interrupt Source TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 TPU channel 4 TGIA_4 TGIB_4 TCIV_4 TCIU_4 TPU channel 5 TGIA_5 TGIB_5 TCIV_5 TCIU_5 8-bit timer channel 0 CMIA_0 CMIB_0 OVI_0 8-bit timer channel 1 CMIA_1 CMIB_1 OVI_1 SCI channel 0 ERI_0 RXI_0 TXI_0 TEI_0 SCI channel 2 ERI_2 RXI_2 TXI_2 TEI_2 Vector Number 48 49 50 51 52 56 57 58 59 60 61 62 63 64 65 66 68 69 70 80 81 82 83 88 89 90 91 Advanced Mode H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC H'0100 H'0104 H'0108 H'0110 H'0114 H'0118 H'0140 H'0144 H'0148 H'014C H'0160 H'0164 H'0168 H'016C Low IPRK2 to IPRK0 IPRJ2 to IPRJ0 IPRI2 to IPRI0 IPRI6 to IPRI4 IPRH2 to IPRH0 IPRH6 to IPRH4 IPR IPRG2 to IPRG0 Priority High
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Section 5 Interrupt Controller Vector Address* Interrupt Source 8-bit timer channel 2 Origin of Interrupt Source CMIA_2 CMIB_2 OVI_2 8-bit timer channel 3 CMIA_3 CMIB_3 OVI_3 HCAN ERS0, OVR0 RM0 RM1 SLE0 SSU channel 0 SSEr_i0 SSRx_i0 SSTx_i0 SSU channel 1 Note: * SSERT_i1 Vector Number 92 93 94 96 97 98 104 105 106 107 108 109 110 111 Advanced Mode H'0170 H'0174 H'0178 H'0180 H'0184 H'0188 H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 H'01B8 H'01BC Low IPRM2 to IPRM0 IPRM6 to IPRM4 IPR IPRL6 to IPRL4 Priority High
Lower 16 bits of the start address.
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Section 5 Interrupt Controller
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes
Interrupt Mask Bits Description I The priorities of interrupt sources are fixed at the default settings. Interrupt sources, except for NMI, are masked by the I bit. 8 priority levels other than NMI can be set with IPR. 8-level interrupt mask control is performed by bits I2 to I0.
Interrupt Priority Setting Control Mode Registers 0 Default
2
IPR
I2 to I0
5.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests other than for NMI are masked by the I bit in CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. If the I bit in CCR is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared, an interrupt request is accepted. 3. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels is selected and other interrupt requests are held pending. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
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Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
Program execution status
Interrupt generated? Yes Yes
No
NMI No I=0 Yes No Hold pending
IRQ0 Yes
No
IRQ1 Yes
No
TEI_2 Yes
Save PC and CCR I1
Read vector address
Branch to interrupt handling routine
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0
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Section 5 Interrupt Controller
5.6.2
Interrupt Control Mode 2
In interrupt control mode 2, mask control is applied to eight levels for interrupt requests other than NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.2 is selected. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
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Section 5 Interrupt Controller
Program execution status
Interrupt generated? Yes Yes NMI No No
No
Level 7 interrupt? Yes Mask level 6 or below? Yes
Level 6 interrupt? No Yes
No
Level 1 interrupt? Mask level 5 or below? Yes Mask level 0? Yes No Yes
No
No
Save PC, CCR, and EXR
Hold pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 5.6.3 Interrupt Exception Handling Sequence
Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
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Interrupt acceptance Internal operation stack Vector fetch Internal operation
Interrupt level determination Instruction Wait for end of instruction prefetch
Interrupt service routine instruction prefetch
Section 5 Interrupt Controller
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(1) (3) (5) (7) (9) (11) (13) (2) (4) (6) (8) (10) (12) (14) (6) (8) (9) (11) (10) (12) (13) (14) Saved PC and saved CCR Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine
Interrupt request signal
Internal address bus
Internal read signal
Internal write signal
Figure 5.5 Interrupt Exception Handling
Internal data bus
(1)
Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address) (2) (4) Instruction code (Not executed) (3) Instruction prefetch address (Not executed) (5) SP-2 (7) SP-4
Section 5 Interrupt Controller
5.6.4
Interrupt Response Times
Table 5.4 shows interrupt response times--the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, has the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.4 Interrupt Response Times
Normal Mode*5 Interrupt control mode 0 3 Interrupt control mode 2 3 Advanced Mode Interrupt control mode 0 3 Interrupt control mode 2 3
No. 1 2 3 4 5 6
Execution Status Interrupt priority determination*1
Number of wait states until executing 19 to 1+2*SI 19 to 1+2*SI instruction ends*2 PC, CCR, EXR stack save Vector fetch Instruction fetch*3 Internal processing*4 2*SK SI 2*SI 2 31 to 11 3*SK SI 2*SI 2 32 to 12
19 to 1+2*SI 19 to 1+2*SI 2*SK 2*SI 2*SI 2 32 to 12 3*SK 2*SI 2*SI 2 33 to 13
Total (using on-chip memory) Notes: 1. 2. 3. 4. 5.
Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in this LSI.
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Section 5 Interrupt Controller
Table 5.5
Number of States in Interrupt Handling Routine Execution Status
Object of Access External Device* 8-Bit Bus 16-Bit Bus 2-State Access 2 3-State Access 3+m
Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK
Internal Memory 1
2-State Access 4
3-State Access 6+2m
Legend: m: Number of wait states in an external device access. Note: * Not available in this LSI.
5.6.5
DTC Activation by Interrupt
The DTC can be activated by an interrupt. For details, see section 8, Data Transfer Controller (DTC).
5.7
5.7.1
Usage Notes
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in TIER_0 of the TPU is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
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Section 5 Interrupt Controller
TIER_0 write cycle by CPU
TCIV exception handling
Internal address bus
TIER_0 address
Internal write signal
TCIEV
TCFV
TCIV interrupt signal
Figure 5.6 Conflict between Interrupt Generation and Disabling 5.7.2 Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 When Interrupts Are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
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Section 5 Interrupt Controller
5.7.4
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W MOV.W BNE R4,R4 L1
5.7.5
IRQ Interrupt
When operating by clock input, acceptance of input to an IRQ is synchronized with the clock. In software standby mode, the input is accepted asynchronously. For details on the input conditions, see section 23.3.2, Control Signal Timing.
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Section 6 PC Break Controller (PBC)
Section 6 PC Break Controller (PBC)
The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. A block diagram of the PC break controller is shown in figure 6.1.
6.1
Features
* Two break channels (A and B) * 24-bit break address Bit masking possible * Four types of break compare conditions Instruction fetch Data read Data write Data read/write * Bus master Either CPU or CPU/DTC can be selected * The timing of PC break exception handling after the occurrence of a break condition is as follows Immediately before execution of the instruction fetched at the set address (instruction fetch) Immediately after execution of the instruction that accesses data at the set address (data access) * Module stop mode can be set
PBC0000A_000020020300
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Section 6 PC Break Controller (PBC)
BARA
BCRA
Output control
Mask control
Comparator
Internal address
Control logic
Access status
PC break interrupt
Comparator
Match signal
Control logic
Output control
Mask control
BARB
BCRB
Figure 6.1 Block Diagram of PC Break Controller
6.2
Register Descriptions
The PC break controller has the following registers. * * * * Break address register A (BARA) Break address register B (BARB) Break control register A (BCRA) Break control register B (BCRB) Break Address Register A (BARA)
6.2.1
BARA is a 32-bit readable/writable register that specifies the channel A break address.
Bit 31 to 24 Bit Name Initial Value Undefined R/W Description Reserved These bits are read as an undefined value and cannot be modified. 23 to 0 BAA23 to BAA0 H'000000 R/W These bits set the channel A PC break address.
-
-
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Section 6 PC Break Controller (PBC)
6.2.2
Break Address Register B (BARB)
BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA)
BCRA controls channel A PC breaks. BCRA also contains a condition match flag.
Bit 7 Bit Name CMFA Initial Value 0 R/W R/W Description Condition Match Flag A [Setting condition] * * 6 CDA 0 R/W When a condition set for channel A is satisfied When 0 is written to CMFA after reading CMFA = 1 [Clearing condition]
CPU Cycle/DTC Cycle Select A Selects the channel A break condition bus master. 0: CPU 1: CPU or DTC
5 4 3
BAMRA2 BAMRA1 BAMRA0
0 0 0
R/W R/W R/W
Break Address Mask Register A2 to A0 These bits specify which bits of the break address set in BARA are to be masked. 000: BAA23 to BAA0 (All bits are unmasked) 001: BAA23 to BAA1 (Lowest bit is masked) 010: BAA23 to BAA2 (Lower 2 bits are masked) 011: BAA23 to BAA3 (Lower 3 bits are masked) 100: BAA23 to BAA4 (Lower 4 bits are masked) 101: BAA23 to BAA8 (Lower 8 bits are masked) 110: BAA23 to BAA12 (Lower 12 bits are masked) 111: BAA23 to BAA16 (Lower 16 bits are masked)
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Section 6 PC Break Controller (PBC) Bit 2 1 Bit Name CSELA1 CSELA0 Initial Value 0 0 R/W R/W R/W Description Break Condition Select A Selects break condition of channel A. 00: Instruction fetch is used as break condition 01: Data read cycle is used as break condition 10: Data write cycle is used as break condition 11: Data read/write cycle is used as break condition 0 BIEA 0 R/W Break Interrupt Enable A When this bit is 1, the PC break interrupt request of channel A is enabled.
6.2.4
Break Control Register B (BCRB)
BCRB is the channel B break control register. The bit configuration is the same as for BCRA.
6.3
Operation
The operation flow from break condition setting to PC break interrupt exception handling is shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and section 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch
1. Set the break address in BARA. For a PC break caused by an instruction fetch, set the address of the first instruction byte as the break address. 2. Set the break conditions in BCR. Set bit 6 (CDA) to 0 to select the CPU because the bus master must be the CPU for a PC break caused by an instruction fetch. Set the address bits to be masked to bits 5 to 3 (BAMA2 to BAMA0). Set bits 2 and 1 (CSELA1 and CSELA0) to 00 to specify an instruction fetch as the break condition. Set bit 0 (BIEA) to 1 to enable break interrupts. 3. When the instruction at the set address is fetched, a PC break request is generated immediately before execution of the fetched instruction, and the condition match flag (CMFA) is set. 4. After priority determination by the interrupt controller, PC break interrupt exception handling is started.
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Section 6 PC Break Controller (PBC)
6.3.2
PC Break Interrupt Due to Data Access
1. Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack operations and branch address reads are included in data accesses. 2. Set the break conditions in BCRA. Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 5 to 3 (BAMA2 to BAMA0). Set bits 2 and 1 (CSELA1 and CSELA0) to 01, 10, or 11 to specify data access as the break condition. Set bit 0 (BIEA) to 1 to enable break interrupts. 3. After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. 4. After priority determination by the interrupt controller, PC break interrupt exception handling is started. 6.3.3 PC Break Operation at Consecutive Data Transfer
* When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction PC break exception handling is executed after all data transfers have been completed and the EEPMOV.B instruction has ended. * When a PC break interrupt is generated at a DTC transfer address PC break exception handling is executed after the DTC has completed the specified number of data transfers, or after data for which the DISEL bit is set to 1 has been transferred. 6.3.4 Operation in Transitions to Power-Down Modes
The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below. * When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to sleep mode: After execution of the SLEEP instruction, a transition is not made to sleep mode, and PC break exception handling is executed. After execution of PC break exception handling, the instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)). * When the SLEEP instruction causes a transition to software standby mode: After execution of the SLEEP instruction, a transition is made to software standby mode, and PC break exception handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2 (B)).
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Section 6 PC Break Controller (PBC)
SLEEP instruction execution
SLEEP instruction execution
PC break exception handling
Transition to respective mode (B)
Execution of instruction after sleep instruction
(A)
Figure 6.2 Operation in Power-Down Mode Transitions 6.3.5 When Instruction Execution Is Delayed by One State
While the break interrupt enable bit is set to 1, instruction execution is one state later than usual. * For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip ROM or RAM. * When break interrupt by instruction fetch is set, the set address indicates on-chip ROM or RAM space, and that address is used for data access, the instruction will be one state later than in normal operation. * When break interrupt by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip ROM or RAM, the instruction will be one state later than in normal operation. Addressing modes: @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC), @(d:16,PC), @@aa:8 * When break interrupt by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is NOP or SLEEP, or has #xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the instruction will be one state later than in normal operation.
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Section 6 PC Break Controller (PBC)
6.4
6.4.1
Usage Notes
Module Stop Mode Setting
PBC operation can be disabled or enabled using the module stop control register. The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes. 6.4.2 PC Break Interrupts
The PC break interrupt is shared by channels A and B. The channel from which the request was issued must be determined by the interrupt handler. 6.4.3 CMFA and CMFB
The CMFA and CMFB flags are not automatically cleared to 0, so 0 must be written to CMFA or CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be requested after interrupt handling ends. 6.4.4 PC Break Interrupt when DTC Is Bus Master
A PC break interrupt generated when the DTC is the bus master is accepted after the bus mastership has been transferred to the CPU by the bus controller. 6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction
Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address. 6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction
When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt becomes valid two states after the end of the instruction execution. If a PC break interrupt is set for the instruction following one of these instructions, since interrupts, including NMI, are disabled for a 3-state period in the case of LDC, ANDC, ORC, and XOR, the next instruction is always executed. For details, see section 5, Interrupt Controller.
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Section 6 PC Break Controller (PBC)
6.4.7
PC Break Set for Instruction Fetch at Address Following Bcc Instruction
A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, and is not generated if the instruction at the next address is not executed. 6.4.8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc Instruction
A PC break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, and is not generated if the instruction at the branch destination is not executed.
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Section 7 Bus Controller
Section 7 Bus Controller
The H8S/2600 CPU is driven by a system clock, denoted by the symbol . The bus controller controls a memory cycle and a bus cycle. Different methods are used to access on-chip memory and on-chip support modules. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC).
7.1
Basic Timing
The period from one rising edge of to the next is referred to as a "state". The memory cycle or bus cycle consists of one, two, three, or four states. Different methods are used to access on-chip memory and on-chip support modules. 7.1.1 On-Chip Memory Access Timing (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 7.1 shows the on-chip memory access cycle.
Bus cycle T1 Internal address bus Address
Internal read signal Read Internal data bus Read data
Internal write signal Write Internal data bus Write data
Figure 7.1 On-Chip Memory Access Cycle
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Section 7 Bus Controller
7.1.2
On-Chip Support Module Access Timing
The on-chip support modules, except for the HCAN, SSU, and realtime input port data register, are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. For details, refer to section 22, List of Registers. Figure 7.2 shows access timing for the on-chip peripheral modules.
Bus cycle T1 Internal address bus Address T2
Internal read signal Read Internal data bus Read data
Internal write signal Write Internal data bus Write data
Figure 7.2 On-Chip Support Module Access Cycle
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Section 7 Bus Controller
7.1.3
On-Chip HCAN Module Access Timing
On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access timing is shown in figure 7.3.
Bus cycle T1 Internal address bus Address T2 T3 Tw Tw T4
HCAN read signal Read Internal data bus Read data
HCAN write signal Write Internal data bus Write data
Figure 7.3 On-Chip HCAN Module Access Cycle (with Wait States)
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Section 7 Bus Controller
7.1.4
On-Chip SSU Module and Realtime Input Port Data Register Access Timing
The on-chip SSU module or realtime input port data register is accessed in three states. At this time, a data bus width is 16 bits. Figure 7.4 shows the SSU module access timing.
Bus cycle T1 Internal address bus Address T2 T3
SSU read signal Read Internal data bus Read data
SSU write signal Write Internal data bus Write data
Figure 7.4 On-Chip SSU Module Access Cycle
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Section 7 Bus Controller
7.2
Bus Arbitration
The Bus Controller has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC, which perform read/write operations when they control the bus. 7.2.1 Order of Priority of the Bus Masters
Each bus master requests the bus mastership by means of a bus request signal. The bus arbiter detects the bus masters' bus request signals, and if the bus mastership is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is cancelled. The order of priority of the bus mastership is as follows: (High) 7.2.2 DTC > CPU (Low)
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus mastership and is currently operating, the bus mastership is not necessarily transferred immediately. The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus mastership to the bus master that issued the request. The timing for transfer of the bus mastership is as follows: * The bus mastership is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus mastership is not transferred between such operations. For details, refer to section 2.7, Bus Status in Instruction Execution in the H8S/2600 Series, H8S/2000 Series Programming Manual. * If the CPU is in sleep mode, it transfers the bus mastership immediately. The DTC can release the bus mastership after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus mastership during a register information read (3 states), a single data transfer, or a register information write (3 states).
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Section 7 Bus Controller
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Section 8 Data Transfer Controller (DTC)
Section 8 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information.
8.1
Features
* Transfer is possible over any number of channels * Three transfer modes Normal, repeat, and block transfer modes are available * One activation source can trigger a number of data transfers (chain transfer) * The direct specification of 16-Mbyte address space is possible * Activation by software is possible * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC * Module stop mode can be set
DTCH80BA_010020020900
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Section 8 Data Transfer Controller (DTC)
Internal address bus On-chip RAM
Interrupt controller
DTC
DTCERA to DTCERG
Control logic
Interrupt request
CPU interrupt request Legend: MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERG: DTVECR:
DTC service request
DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC destination address register DTC enable registers A to G DTC vector register
Figure 8.1 Block Diagram of DTC
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MRA MRB CRA CRB DAR SAR
Internal data bus
Register information
DTVECR
Section 8 Data Transfer Controller (DTC)
8.2
Register Descriptions
The DTC has the following registers. * * * * * * DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set of register information that is stored in on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to the RAM. * DTC enable registers (DTCER) * DTC vector register (DTVECR)
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Section 8 Data Transfer Controller (DTC)
8.2.1
DTC Mode Register A (MRA)
MRA is an 8-bit register that selects the DTC operating mode.
Bit 7 6 Bit Name SM1 SM0 Initial Value Undefined Undefined R/W Description Source Address Mode 1 and 0 These bits specify an SAR operation after a data transfer. 0x: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 5 4 DM1 DM0 Undefined Undefined

Destination Address Mode 1 and 0 These bits specify a DAR operation after a data transfer. 0x: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1)
3 2
MD1 MD0
Undefined Undefined

DTC Mode These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited
1
DTS
Undefined
DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area
0
Sz
Undefined
DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer
Legend: x: Don't care
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Section 8 Data Transfer Controller (DTC)
8.2.2
DTC Mode Register B (MRB)
MRB is an 8-bit register that selects the DTC operating mode.
Bit 7 Bit Name CHNE Initial Value Undefined R/W Description DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to 8.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER, are not performed. 6 DISEL Undefined
DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time after the end of a data transfer. When this bit is set to 0, a CPU interrupt request is generated at the time when the specified number of data transfer ends.
5 to 0
Undefined
Reserved These bits have no effect on DTC operation. Only 0 should be written to these bits.
8.2.3
DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 8.2.5 DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
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Section 8 Data Transfer Controller (DTC)
In repeat mode or block transfer mode, the CRA is divided into two parts; the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 8.2.6 DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 8.2.7 DTC Enable Registers (DTCER)
DTCER is comprised of seven registers; DTCERA to DTCERG, and is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 8.1. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register.
Bit 7 6 5 4 3 2 1 0 Bit Name DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Activation Enable Setting these bits to 1 specifies a relevant interrupt source as a DTC activation source. [Clearing conditions] * * When the DISEL bit in MRB is 1 and the data transfer has ended When the specified number of transfers have ended
These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not been completed.
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Section 8 Data Transfer Controller (DTC)
8.2.8
DTC Vector Register (DTVECR)
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt.
Bit 7 Bit Name SWDTE Initial Value 0 R/W R/W Description DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit. [Clearing conditions] * * When the DISEL bit is 0 and the specified number of transfers have not ended When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU.
When the DISEL bit is 1 and data transfer has ended or when the specified number of transfers have ended, this bit will not be cleared. 6 5 4 3 2 1 0 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W DTC Software Activation Vectors 6 to 0 These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + (vector number x 2). For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. When the bit SWDTE is 0, these bits can be written.
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Section 8 Data Transfer Controller (DTC)
8.3
Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of RXI_0, for example, is the RDRF flag of SCI_0. When an interrupt has been designated a DTC activation source, the existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Figure 8.2 shows a block diagram of DTC activation source control. For details, see section 5, Interrupt Controller.
Source flag cleared Clear controller Clear DTCER Select Clear request
IRQ interrupt
Interrupt request
Selection circuit
On-chip supporting module
DTC
DTVECR
Interrupt controller Interrupt mask
CPU
Figure 8.2 Block Diagram of DTC Activation Source Control
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Section 8 Data Transfer Controller (DTC)
8.4
Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF). Register information should be located at an address that is a multiple of four within the range. Locating the register information in address space is shown in figure 8.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas and the register information start address should be located at the vector address corresponding to the interrupt source as shown in figure 8.3. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] x 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the register information start address.
Lower address 0 Register information start address MRA MRB Chain transfer CRA MRA MRB CRA SAR DAR CRB Register information for 2nd transfer in chain transfer 1 2 SAR DAR CRB Register information 3
4 bytes
Figure 8.3 Location of DTC Register Information in Address Space
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Section 8 Data Transfer Controller (DTC)
Table 8.1
Interrupt Source Software External pin
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of Interrupt Source Write to DTVECR IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved for system use Vector Number DTVECR 16 17 18 19 20 21 22 23 DTC Vector Address H'0400 + (vector number x 2) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0438 H'0440 H'0442 H'0444 H'0446 H'0450 H'0452 H'0458 H'045A H'0460 H'0462 H'0464 H'0466 H'0470 H'0472 H'0478 H'047A DTCE* DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED5 DTCED4 Low Priority High
A/D counter TPU channel 0
ADI (A/D conversion 28 end) TGIA_0 TGIB_0 TGIC_0 TGID_0 32 33 34 35 40 41 44 45 48 49 50 51 56 57 60 61
TPU channel 1 TPU channel 2 TPU channel 3
TGIA_1 TGIB_1 TGIA_2 TGIB_2 TGIA_3 TGIB_3 TGIC_3 TGID_3
TPU channel 4 TPU channel 5
TGIA_4 TGIB_4 TGIA_5 TGIB_5
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Section 8 Data Transfer Controller (DTC) Interrupt Source 8-bit timer channel 0 8-bit timer channel 1 Origin of Interrupt Source CMIA_1 DTC Vector Address H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'0494 H'0496 H'04A2 H'04A4 H'04B2 H'04B4 H'04B8 H'04BA H'04C0 H'04C2 H'04D0 H'04D2 H'04D4 H'04D6 H'04DA H'04DC
Vector Number 64 65
DTCE* DTCED3 DTCED2 DTCED1 DTCED0 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEG7 DTCEG6 DTCEG5 DTCEG4 DTCEG2 DTCEG1
Priority High
CMIB_1
68 69
Reserved
72 73 74 75
SCI channel 0 SCI channel 2 8-bit timer channel 2 8-bit timer channel 3 HCAN
RXI_0 TXI_0 RXI_2 TXI_2 CMIA_2 CMIB_2 CMIA_3 CMIB3
81 82 89 90 92 93 96 97
Reserved for system 104 use RM0 105
Reserved for system 106 use Reserved for system 107 use SSU channel 0 Note: * SSRx_i0 SSTx_i0 109 110
Low
DTCE bits with no corresponding interrupt are reserved, and the write value should aslways be 0.
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Section 8 Data Transfer Controller (DTC)
8.5
Operation
Register information is stored in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to the on-chip RAM. The pre-storage of register information in the on-chip RAM makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, and block transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed depending on its register information.
Start
Read DTC vector Next transfer
Read register information
Data transfer
Write register information
CHNE=1 No
Yes
Transfer Counter=0 or DISEL=1 No Clear an activation flag
Yes
Clear DTCER
End
Interrupt exception handling
Figure 8.4 Flowchart of DTC Operation
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Section 8 Data Transfer Controller (DTC)
8.5.1
Normal Mode
In normal mode, one operation transfers one byte or one word of data. Table 8.2 lists the register information in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt can be requested. Table 8.2
Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B
Register Information in Normal Mode
Abbreviation SAR DAR CRA CRB Function Designates source address Designates destination address Designates transfer count Not used
SAR Transfer
DAR
Figure 8.5 Memory Mapping in Normal Mode
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Section 8 Data Transfer Controller (DTC)
8.5.2
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data. Table 8.3 lists the register information in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 8.3
Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B
Register Information in Repeat Mode
Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds number of transfers Designates transfer count Not used
SAR or DAR
Repeat area Transfer
DAR or SAR
Figure 8.6 Memory Mapping in Repeat Mode
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Section 8 Data Transfer Controller (DTC)
8.5.3
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 8.4 lists the register information in block transfer mode. The block size can be between 1 and 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt is requested. Table 8.4
Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B
Register Information in Block Transfer Mode
Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds block size Designates block size count Transfer count
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Section 8 Data Transfer Controller (DTC)
First block
SAR or DAR
. . . Transfer
Block area
DAR or SAR
Nth block
Figure 8.7 Memory Mapping in Block Transfer Mode
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Section 8 Data Transfer Controller (DTC)
8.5.4
Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.8 shows the outline of the chain transfer operation. When activated, the DTC reads the register information start address stored at the vector address corresponding to the activation source, and then reads the first register information at that start address. After data transfer ends, the CHNE bit will be tested. When it has been set to 1, DTC reads the next register information located in a consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected.
Source
Destination
Register information CHNE=1
DTC vector address
Register information start address
Register information CHNE=0
Source
Destination
Figure 8.8 Chain Transfer Operation
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Section 8 Data Transfer Controller (DTC)
8.5.5
Interrupts
An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has been completed, or the specified number of transfers have been completed, after data transfer ends the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 8.5.6
DTC activation request DTC request Data transfer
Read Write
Operation Timing
Vector read Address
Transfer information read
Transfer information write
Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
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Section 8 Data Transfer Controller (DTC)
DTC activation request DTC request Vector read Address Data transfer
Read Write Read Write
Transfer information read
Transfer information write
Figure 8.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)
DTC activation request DTC request Vector read Address
Read Write Read Write
Data transfer
Data transfer
Transfer information read
Transfer information write
Transfer information read
Transfer information write
Figure 8.11 DTC Operation Timing (Example of Chain Transfer) 8.5.7 Number of DTC Execution States
Table 8.5 lists execution status for a single DTC data transfer, and table 8.6 shows the number of states required for each execution status.
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Section 8 Data Transfer Controller (DTC)
Table 8.5
DTC Execution Status
Vector Read I 1 1 1 Register Information Read/Write Data Read J K 6 6 6 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3
Mode Normal Repeat Block transfer
Legend: N: Block size (initial setting of CRAH and CRAL)
Table 8.6
Number of States Required for Each Execution Status
OnChip RAM 32 1 SI 1 1 1 1 1 OnChip ROM 16 1 1 1 1 1 1 On-Chip I/O Registers 8 2 2 4 2 4 16 2 2 2 2 2 1 2 4 2 4 2 4 External Devices* 8 3 6+2m 3+m 6+2m 3+m 6+2m 2 2 2 2 2 2 16 3 3+m 3+m 3+m 3+m 3+m
Object to be Accessed Bus width Access states Execution status Vector read
Register information read/write SJ Byte data read Word data read Byte data write Word data write Internal operation SK SK SL SL SM
Note:
*
Not available in this LSI.
The number of execution states is calculated from using the formula below. Note that is the sum of all transfers activated by one activation source (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * (1 + SI) + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in the on-chip ROM, normal mode is set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
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Section 8 Data Transfer Controller (DTC)
8.6
8.6.1
Procedures for Using DTC
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows: 1. 2. 3. 4. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. Set the start address of the register information in the DTC vector address. Set the corresponding bit in DTCER to 1. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After one data transfer has been completed, or after the specified number of data transfers have been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. 8.6.2 Activation by Software
The procedure for using the DTC with software activation is as follows: 1. 2. 3. 4. 5. 6. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. Set the start address of the register information in the DTC vector address. Check that the SWDTE bit is 0. Write 1 to SWDTE bit and the vector number to DTVECR. Check the vector number written to DTVECR. After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested.
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Section 8 Data Transfer Controller (DTC)
8.7
8.7.1
Examples of Use of the DTC
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have been completed, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine will perform wrap-up processing.
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Section 8 Data Transfer Controller (DTC)
8.7.2
Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). 1. Perform settings for transfer to the PPG's NDR. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), a fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. 2. Perform settings for transfer to the TPU's TGR. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), a fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. 3. Locate the TPU transfer register information consecutively after the NDR transfer register information. 4. Set the start address of the NDR transfer register information to the DTC vector address. 5. Set the bit corresponding to TGIA in DTCER to 1. 6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. 7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. 8. Set the CST bit in TSTR to 1, and start the TCNT count operation. 9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine.
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Section 8 Data Transfer Controller (DTC)
8.7.3
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing.
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Section 8 Data Transfer Controller (DTC)
8.8
8.8.1
Usage Notes
Module Stop Mode Setting
DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting module stop mode. Note that module stop mode cannot be set during DTC being activated. For details, refer to section 21, Power-Down Modes. 8.8.2 On-Chip RAM
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. 8.8.3 DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register.
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Section 8 Data Transfer Controller (DTC)
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Section 9 I/O Ports
Section 9 I/O Ports
Table 9.1 summarizes the port functions. The pins of each port also have other functions such as input/output or interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR or DDR register. Ports A to D have built-in input pull-up MOS functions and input pull-up MOS control registers (PCR) to control the on/off state of input pull-up MOS. Ports A to C include an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. All the I/O ports can drive a single TTL load and a 30 pF capacitive load.
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Section 9 I/O Ports
Table 9.1
Port Port 1
Port Functions
Description General I/O port also functioning as TPU_2, TPU_1, and TPU_0 I/O pins, PPG output pins, and interrupt input pins Port and Other Functions Name P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 Input/Output and Output Type
Port 3
General I/O port also functioning as SCI_0 I/O pins and interrupt input pins
P37 P36 P35/IRQ5 P34 P33 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0
Port 4
General input port also P47/AN7 functioning as A/D P46/AN6 converter analog P45/AN5 inputs P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
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Section 9 I/O Ports Port and Other Functions Name P77 P76 P75/TMO3 P74/TMO2 P73/TMO1 P72/TMO0 P71/TMCI23/TMRI23 P70/TMCI01/TMRI01 Port 9 General input port also P97/AN15 functioning as A/D P96/AN14 converter analog P95/AN13 inputs P94/AN12 P93/AN11 P92/AN10 P91/AN9 P90/AN8 Port A General I/O port also functioning as SCI_2 I/O pins PA3/SCK2 PA2/RxD2 PA1/TxD2 PA0 Port B General I/O port also functioning as TPU_5, TPU_4, and TPU_3 I/O pins PB7/TIOCB5 PB6/TIOCA5 PB5/TIOCB4 PB4/TIOCA4 PB3/TIOCD3 PB2/TIOCC3 PB1/TIOCB3 PB0/TIOCA3 Built-in input pull-up MOS Push-pull or open-drain output selectable Built-in input pull-up MOS Push-pull or open-drain output selectable Input/Output and Output Type
Port Port 7
Description General I/O port also functioning as TMR_0, TMR_1, TMR_2, and TMR_3 I/O pins
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Section 9 I/O Ports Port and Other Functions Name PC7/SCS1 PC6/SSCK1 PC5/SSI1 PC4/SSO1 PC3/SCS0 PC2/SSCK0 PC1/SSI0 PC0/SSO0 Port D General I/O port PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port F General I/O port also functioning as interrupt input pins, an A/D converter start trigger input pin, and a system clock output pin () PF7/ PF6 PF5 PF4 PF3/ADTRG/IRQ3 PF2 PF1 PF0/IRQ2 Built-in input pull-up MOS Input/Output and Output Type Built-in input pull-up MOS Push-pull or open-drain output selectable
Port Port C
Description General I/O port also functioning as SSU_0 and SSU_1 I/O pins
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Section 9 I/O Ports
9.1
Port 1
Port 1 is an 8-bit I/O port and has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 register (PORT1) 9.1.1 Port 1 Data Direction Register (P1DDR)
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin is specified as a general purpose I/O port, setting these bits to 1 makes the corresponding port 1 pin an output pin. Clearing these bits to 0 makes the pin an input pin.
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Section 9 I/O Ports
9.1.2
Port 1 Data Register (P1DR)
P1DR is an 8-bit readable/writable register that stores output data for port 1 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin is specified as a general purpose I/O port.
9.1.3
Port 1 Register (PORT1)
PORT1 is an 8-bit read-only register that shows the pin states. PORT1 cannot be modified.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P17 P16 P15 P14 P13 P12 P11 P10 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read.
Determined by the states of pins P17 to P10.
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Section 9 I/O Ports
9.1.4
Pin Functions
Port 1 pins also function as TPU I/O pins, PPG output pins, and interrupt input pins. The correspondence between the register specification and the pin functions is shown below. Table 9.2 P17 Pin Function
Output Input or Initial Value 0 1 0 P17 output 1 1 PO15 output
TPU Channel 2 Setting* P17DDR NDER15 Pin function

TIOCB2 output
P17 input TIOCB2 input TCLKD input
Note:
*
For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
Table 9.3
P16 Pin Function
Output Input or Initial Value 0 1 0 P16 output 1 1 PO14 output
TPU Channel 2 Setting* P16DDR NDER14 Pin function

TIOCA2 output
P16 input TIOCA2 input input
Note:
*
For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
1QRI
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Section 9 I/O Ports
Table 9.4
P15 Pin Function
Output Input or Initial Value 0 1 0 P15 output 1 1 PO13 output
TPU Channel 1 Setting* P15DDR NDER13 Pin function

TIOCB1 output
P15 input TIOCB1 input TCLKC input
Note:
*
For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
Table 9.5
P14 Pin Function
Output Input or Initial Value 0 1 0 P14 output 1 1 PO12 output
TPU Channel 1 Setting* P14DDR NDER12 Pin function

TIOCA1 output
P14 input TIOCA1 input input
Note:
*
For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
Table 9.6
P13 Pin Function
Output Input or Initial Value 0 1 0 P13 output 1 1 PO11 output
TPU Channel 0 Setting* P13DDR NDER11 Pin function

TIOCD0 output
P13 input TIOCD0 input TCLKB input
Note:
*
For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
Rev. 3.00 Oct 04, 2005 page 134 of 598 REJ09B0155-0300
0QRI
Section 9 I/O Ports
Table 9.7
P12 Pin Function
Output Input or Initial Value 0 1 0 P12 output 1 1 PO10 output
TPU Channel 0 Setting* P12DDR NDER10 Pin function

TIOCC0 output
P12 input TIOCC0 input TCLKA input
Note:
*
For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
Table 9.8
P11 Pin Function
Output Input or Initial Value 0 1 0 P11 output 1 1 PO9 output
TPU Channel 0 Setting* P11DDR NDER9 Pin function Note: *

TIOCB0 output
P11 input TIOCB0 input
For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
Table 9.9
P10 Pin Function
Output Input or Initial Value 0 1 0 P10 output 1 1 PO8 output
TPU Channel 0 Setting* P10DDR NDER8 Pin function Note: *

TIOCA0 output
P10 input TIOCA0 input
For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
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Section 9 I/O Ports
9.2
Port 3
Port 3 is an 8-bit I/O port and has the following registers. * * * * Port 3 data direction register (P3DDR) Port 3 data register (P3DR) Port 3 register (PORT3) Port 3 open-drain control register (P3ODR) Port 3 Data Direction Register (P3DDR)
9.2.1
P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3.
Bit 7 6 5 4 3 2 1 0 Bit Name P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin is specified as a general purpose I/O port, setting these bits to 1 makes the corresponding port 3 pin an output pin. Clearing these bits to 0 makes the pin an input pin.
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Section 9 I/O Ports
9.2.2
Port 3 Data Register (P3DR)
P3DR is an 8-bit readable/writable register that stores output data for port 3 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin is specified as a general I/O port.
9.2.3
Port 3 Register (PORT3)
PORT3 is an 8-bit read-only register that shows the pin states.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P37 P36 P35 P34 P33 P32 P31 P30 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read.
Determined by the states of pins P37 to P30.
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Section 9 I/O Ports
9.2.4
Port 3 Open-Drain Control Register (P3ODR)
P3ODR is an 8-bit readable/writable register that specifies the output type of port 3.
Bit 7 6 5 4 3 2 1 0 Bit Name P37ODR P36ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin is specified as an output port, setting the corresponding bits to 1 specifies pin output to opendrain and the input pull-up MOS to the off state. Clearing these bits to 0 specifies that to push-pull output.
9.2.5
Pin Functions
Port 3 pins also function as SCI_0 I/O pins and interrupt input pins. The correspondence between the register specification and the pin functions is shown below. Table 9.10 P37 Pin Function
P37DDR Pin function 0 P37 input 1 P37 output
Table 9.11 P36 Pin Function
P36DDR Pin function 0 P36 input 1 P36 output
Table 9.12 P35 Pin Function
P35DDR Pin function 0 P35 input input*
5QRI
1 P35 output
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Section 9 I/O Ports
Table 9.13 P34 Pin Function
P34DDR Pin function 0 P34 input 1 P34 output
Table 9.14 P33 Pin Function
P33DDR Pin function 0 P33 input 1 P33 output
Table 9.15 P32 Pin Function
CKE1 in SCR_0 C/A in SMR_0 CKE0 in SCR_0 P32DDR Pin function 0 P32 input 0 1 P32 output 0 1 0 1 1
SCK0 output input*
4QRI

SCK0 output

SCK0 input
Table 9.16 P31 Pin Function
RE in SCR_0 P31DDR Pin function 0 P31 input 0 1 P31 output 1
RxD0 output
Table 9.17 P30 Pin Function
TE in SCR_0 P30DDR Pin function Note: * 0 P30 input 0 1 P30 output 1
TxD0 output
When used as an external interrupt input pin, do not use as an I/O pin for another function.
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Section 9 I/O Ports
9.3
Port 4
Port 4 is an input-only port. Port 4 pins also function as A/D converter analog input pins. Port 4 has the following register. * Port 4 register (PORT4) 9.3.1 Port 4 Register (PORT4)
PORT4 is an 8-bit read-only register that shows port 4 pin states.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P47 P46 P45 P44 P43 P42 P41 P40 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description The pin states are always read when a port 4 read is performed.
Determined by the states of pins P47 to P40.
9.4
Port 7
Port 7 is an 8-bit I/O port and has the following registers. * Port 7 data direction register (P7DDR) * Port 7 data register (P7DR) * Port 7 register (PORT7)
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Section 9 I/O Ports
9.4.1
Port 7 Data Direction Register (P7DDR)
P7DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 7. P7DDR cannot be read, if it is, an undefined value will be read.
Bit 7 6 5 4 3 2 1 0 Bit Name P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin is specified as a general purpose I/O port, setting these bits to 1 makes the corresponding port 7 pin an output pin. Clearing these bits to 0 makes the pin an input pin.
9.4.2
Port 7 Data Register (P7DR)
P7DR is an 8-bit readable/writable register that stores output data for port 7 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name P77DR P76DR P75DR P74DR P73DR P72DR P71DR P70DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin is specified as a general purpose I/O port.
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Section 9 I/O Ports
9.4.3
Port 7 Register (PORT7)
PORT7 is an 8-bit read-only register that shows the pin states. PORT7 cannot be modified.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P77 P76 P75 P74 P73 P72 P71 P70 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port 7 read is performed while P7DDR bits are set to 1, the P7DR values are read. If a port 7 read is performed while P7DDR bits are cleared to 0, the pin states are read.
Determined by the states of pins P77 to P70.
9.4.4
Pin Functions
Port 7 pins also function as TMR_3, TMR_2, TMR_1, and TMR_0 I/O pins. The correspondence between the register specification and the pin functions is shown below. Table 9.18 P77 Pin Function
P77DDR Pin function 0 P77 input 1 P77 output
Table 9.19 P76 Pin Function
P76DDR Pin function 0 P76 input 1 P76 output
Table 9.20 P75 Pin Function
OS3 to OS0 in TCSR_3 P75DDR Pin function 0 P75 input All 0 1 P75 output Any of 1
TMO3 output
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Section 9 I/O Ports
Table 9.21 P74 Pin Function
OS3 to OS0 in TCSR_2 P74DDR Pin function 0 P74 input All 0 1 P74 output Any of 1
TMO2 output
Table 9.22 P73 Pin Function
OS3 to OS0 in TCSR_1 P73DDR Pin function 0 P73 input All 0 1 P73 output Any of 1
TMO1 output
Table 9.23 P72 Pin Function
OS3 to OS0 in TCSR_0 P72DDR Pin function 0 P72 input All 0 1 P72 output Any of 1
TMO0 output
Table 9.24 P71 Pin Function
P71DDR Pin function 0 P71 input 1 P71 output
TMCI23 input/TMRI23 input
Table 9.25 P70 Pin Function
P70DDR Pin function 0 P70 input 1 P70 output
TMCI01 input/TMRI01 input
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Section 9 I/O Ports
9.5
Port 9
Port 9 is an input-only port. Port 9 pins also function as A/D converter analog input pins. Port 9 has the following register. * Port 9 register (PORT9) 9.5.1 Port 9 Register (PORT9)
PORT9 is an 8-bit read-only register that shows port 9 pin states. PORT9 cannot be modified.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name P97 P96 P95 P94 P93 P92 P91 P90 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description The pin states are always read when a port 9 read is performed.
Determined by the states of pins P97 to P90.
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Section 9 I/O Ports
9.6
Port A
Port A is a 4-bit I/O port that also has other functions. Port A has the following registers. * * * * * Port A data direction register (PADDR) Port A data register (PADR) Port A register (PORTA) Port A pull-up MOS control register (PAPCR) Port A open-drain control register (PAODR) Port A Data Direction Register (PADDR)
9.6.1
PADDR is an 8-bit write-only register, the individual bits of which specify whether the pins of port A are used for input or output.
Bit 7 to 4 3 2 1 0 Bit Name Initial Value Undefined R/W Description Reserved These bits are read as undefined value and cannot be modified. PA3DDR PA2DDR PA1DDR PA0DDR 0 0 0 0 W W W W When a pin is specified as a general purpose I/O port, setting these bits to 1 makes the corresponding port A pin an output pin. Clearing these bits to 0 makes the pin an input pin.
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Section 9 I/O Ports
9.6.2
Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores output data for port A pins.
Bit 7 to 4 3 2 1 0 Bit Name Initial Value Undefined R/W Description Reserved These bits are read as an undefined value and cannot be modified. PA3DR PA2DR PA1DR PA0DR 0 0 0 0 R/W R/W R/W R/W Output data for a pin is stored when the pin is specified as a general purpose I/O port.
9.6.3
Port A Register (PORTA)
PORTA is an 8-bit read-only register that shows port A pin states.
Bit 7 to 4 3 2 1 0 Note: Bit Name Initial Value Undefined 0 0 0 0 R/W Description Reserved These bits are read as an undefined value. PA3 PA2 PA1 PA0 * R R R R If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read.
Determined by the states of pins PA3 to PA0.
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Section 9 I/O Ports
9.6.4
Port A Pull-Up MOS Control Register (PAPCR)
PAPCR is an 8-bit register that controls the input pull-up MOS function.
Bit 7 to 4 3 2 1 0 Bit Name Initial Value Undefined R/W Description Reserved These bits are read as an undefined value and cannot be modified. PA3PCR PA2PCR PA1PCR PA0PCR 0 0 0 0 R/W R/W R/W R/W When a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
9.6.5
Port A Open-Drain Control Register (PAODR)
PAODR is an 8-bit readable/writable register that specifies the output type of port A.
Bit 7 to 4 3 2 1 0 Bit Name Initial Value Undefined R/W Description Reserved These bits are read as an undefined value and cannot be modified. PA3ODR PA2ODR PA1ODR PA0ODR 0 0 0 0 R/W R/W R/W R/W When a pin is specified as an output port, setting the corresponding bits to 1 specifies pin output to opendrain and the input pull-up MOS to the off state. Clearing these bits to 0 specifies that to push-pull output.
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Section 9 I/O Ports
9.6.6
Pin Functions
Port A pins also function as SCI_2 I/O pins. The correspondence between the register specification and the pin functions is shown below. Table 9.26 PA3 Pin Function
CKE1 in SCR_2 C/A in SMR_2 CKE0 in SCR_2 PA3DDR Pin function 0 PA3 input 0 1 PA3 output 0 1 0 1 1
SCK2 output

SCK2 output

SCK2 input
Table 9.27 PA2 Pin Function
RE in SCR_2 PA2DDR Pin function 0 PA2 input 0 1 PA2 output 1
RxD2 input
Table 9.28 PA1 Pin Function
TE in SCR_2 PA1DDR Pin function 0 PA1 input 0 1 PA1 output 1
TxD2 output
Table 9.29 PA0 Pin Function
PA0DDR Pin function 0 PA0 input 1 PA0 output
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Section 9 I/O Ports
9.7
Port B
Port B is an 8-bit I/O port that also has other functions. Port B has the following registers. * * * * * Port B data direction register (PBDDR) Port B data register (PBDR) Port B register (PORTB) Port B pull-up MOS control register (PBPCR) Port B open-drain control register (PBODR) Port B Data Direction Register (PBDDR)
9.7.1
PBDDR is an 8-bit write-only register, the individual bits of which specify whether the pins of port B are used for input or output.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin is specified as a general purpose I/O port, setting these bits to 1 makes the corresponding port 1 pin an output pin. Clearing these bits to 0 makes the pin an input pin.
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Section 9 I/O Ports
9.7.2
Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores output data for the port B pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin is specified as a general purpose I/O port.
9.7.3
Port B Register (PORTB)
PORTB is an 8-bit read-only register that shows port B pin states.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 * Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read.
Determined by the states of pins PB7 to PB0.
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Section 9 I/O Ports
9.7.4
Port B Pull-Up MOS Control Register (PBPCR)
PBPCR is an 8-bit readable/writable register that controls the on/off state of input pull-up MOS of port B.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin is specified as an input port, setting the corresponding bits to 1 turns on the input pull-up MOS for that pin.
9.7.5
Port B Open-Drain Control Register (PBODR)
PBODR is an 8-bit readable/writable register that specifies the output type of port B.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin function is specified as an output port, setting the corresponding bits to 1 specifies pin output as open-drain and the input pull-up MOS to the off state. Clearing these bits to 0 specifies pushpull output.
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Section 9 I/O Ports
9.7.6
Pin Functions
Port B pins also function as TPU I/O pins. The correspondence between the register specification and the pin functions is shown below. Table 9.30 PB7 Pin Function
TPU channel 5 setting* PB7DDR Pin function Note: * Output Input or Initial Value 0 PB7 input 1 PB7 output TIOCB5 input For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
TIOCB5 output
Table 9.31 PB6 Pin Function
TPU channel 5 setting* PB6DDR Pin function Note: * Output Input or Initial Value 0 PB6 input 1 PB6 output TIOCA5 input For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
TIOCA5 output
Table 9.32 PB5 Pin Function
TPU channel 4 setting* PB5DDR Pin function Note: * Output Input or Initial Value 0 PB5 input 1 PB5 output TIOCB4 input For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
TIOCB4 output
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Section 9 I/O Ports
Table 9.33 PB4 Pin Function
TPU channel 4 setting* PB4DDR Pin function Note: * Output Input or Initial Value 0 PB4 input 1 PB4 output TIOCA4 input For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
TIOCA4 output
Table 9.34 PB3 Pin Function
TPU channel 3 setting* PB3DDR Pin function Note: * Output Input or Initial Value 0 PB3 input 1 PB3 output TIOCD3 input For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
TIOCD3 output
Table 9.35 PB2 Pin Function
TPU channel 3 setting* PB2DDR Pin function Note: * Output Input or Initial Value 0 PB2 input 1 PB2 output TIOCC3 input For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
TIOCC3 output
Table 9.36 PB1 Pin Function
TPU channel 3 setting* PB1DDR Pin function Note: * Output Input or Initial Value 0 PB1 input 1 PB1 output TIOCB3 input For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
TIOCB3 output
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Section 9 I/O Ports
Table 9.37 PB0 Pin Function
TPU channel 3 setting* PB0DDR Pin function Note: * Output Input or Initial Value 0 PB0 input 1 PB0 output TIOCA3 input For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU).
TIOCA3 output
9.8
Port C
Port C is an 8-bit I/O port that also has other functions. Port C has the following registers. * * * * * Port C data direction register (PCDDR) Port C data register (PCDR) Port C register (PORTC) Port C pull-up MOS control register (PCPCR) Port C open-drain control register (PCODR) Port C Data Direction Register (PCDDR)
9.8.1
PCDDR is an 8-bit write-only register, the individual bits of which specify whether the pins of port C are used for input or output.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin is specified as a general purpose I/O port, setting these bits to 1 makes the corresponding port 1 pin an output pin. Clearing these bits to 0 makes the pin an input pin.
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Section 9 I/O Ports
9.8.2
Port C Data Register (PCDR)
PCDR is an 8-bit readable/writable register that stores output data for the port C pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin is specified as a general purpose I/O port.
9.8.3
Port C Register (PORTC)
PORTC is an 8-bit read-only register that shows port C pin states.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 * Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read.
Determined by the states of pins PC7 to PC0.
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Section 9 I/O Ports
9.8.4
Port C Pull-Up MOS Control Register (PCPCR)
PCPCR is an 8-bit readable/writable register that controls the on/off state of input pull-up MOS of port C.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin is specified as an input port, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
9.8.5
Port C Open-Drain Control Register (PCODR)
PCODR is an 8-bit readable/writable register that specifies an output type of port C.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a pin is specified as an output port, setting the corresponding bits to 1 specifies pin output as opendrain and the input pull-up MOS to the off state. Clearing these bits to 0 specifies push-pull output.
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Section 9 I/O Ports
9.8.6
Pin Functions
Port C pins also function as SSU_1 and SSU_0 I/O pins. The correspondence between the register specification and the pin functions is shown below. Table 9.38 PC7 Pin Function
CSS1 CSS0 PC7DDR Pin function 0 PC7 input 0 1 PC7 output 0 1 0 1 1
input
1SCS
input/output auto switch
1SCS
output
1SCS
Table 9.39 PC6 Pin Function
MSS SCKS PC6DDR Pin function 0 PC6 input 0 1 PC6 output 0 1 1 1 0
SSCK1 input
SSCK1 output
Setting prohibited
Table 9.40 PC5 Pin Function
MSS BIDE RE TE PC5DDR input PC5 input 0 PC5 output 0 1 0 SSI1 output 0 1 1 SSI1 Hi-Z PC5 input PC5 output PC5 input 0 1 0 0 1 0 1 PC5 output SSI1 input PC5 input PC5 output 0 0 1 1 1 1
1SCS
Pin function
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Section 9 I/O Ports
Table 9.41 PC4 Pin Function
MSS BIDE RE TE PC4DDR input 0 0 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 1 1 1 0 1 0 1
Table 9.42 PC3 Pin Function
CSS1 CSS0 PC3DDR Pin function 0 PC3 input 0 1 PC3 output 0 1 0 1 1
input/output auto switch
Table 9.43 PC2 Pin Function
MSS SCKS PC2DDR Pin function 0 PC2 input 0 1 PC2 output 0 1 1 1 0
SSCK0 input
SSCK0 output
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0SCS
0SCS
0SCS
1SCS
Pin function
PC4 PC4 SSO1 PC4 PC4 SSO1 PC4 PC4 SSO1 Setting SSO1 SSO1 SSO1 input output input input output output input output input pro- output Hi-Z output hibited
input
output
Setting prohibited
Section 9 I/O Ports
Table 9.44 PC1 Pin Function
MSS BIDE RE TE PC1DDR input PC1 input 0 PC1 output 0 1 0 SSI0 output 0 1 1 SSI0 Hi-Z PC1 input PC1 output PC1 input 0 1 0 0 1 0 1 PC1 output SSI0 input PC1 input PC1 output 0 0 1 1 1 1
Table 9.45 PC0 Pin Function
MSS BIDE RE TE PC0DDR input 0 0 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 1 1 1 0 1 0 1
0SCS 0SCS
Pin function
Pin function
PC0 PC0 SSO0 PC0 PC0 SSO0 PC0 PC0 SSO0 Setting SSO0 SSO0 SSO0 input output input input output output input output input pro- output Hi-Z output hibited
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Section 9 I/O Ports
9.9
Port D
Port D is an 8-bit I/O port that also functions as the realtime input port pins. pin as the The realtime input port stores the pin states of port D in PDRTIDR using the pin can be used as a trigger timing. trigger input. The falling, rising, or both edges of the Port D has the following registers. * * * * * Port D data direction register (PDDDR) Port D data register (PDDR) Port D register (PORTD) Port D pull-up MOS control register (PDPCR) Port D realtime input data register (PDRTIDR) Port D Data Direction Register (PDDDR)
3QRI 3QRI
9.9.1
PDDDR is an 8-bit write-only register, the individual bits of which specify whether the pins of port D are used for input or output.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description When a pin is specified as a general purpose I/O port, setting these bits to 1 makes the corresponding port 1 pin an output pin. Clearing these bits to 0 makes the pin an input pin.
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Section 9 I/O Ports
9.9.2
Port D Data Register (PDDR)
PDDR is an 8-bit readable/writable register that stores output data for the port D pins.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output data for a pin is stored when the pin is specified as a general purpose I/O port.
9.9.3
Port D Register (PORTD)
PORTD is an 8-bit read-only register that shows port D pin states.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read.
Determined by the states of pins PD7 to PD0.
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Section 9 I/O Ports
9.9.4
Port D Pull-Up MOS Control Register (PDPCR)
PDPCR is an 8-bit readable/writable register that controls on/off states of the input pull-up MOS of port D.
Bit 7 6 5 4 3 2 1 0 Bit Name PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When the pin is in its input state, the input pull-up MOS of the input pin is on when the corresponding bits are set to 1.
9.9.5
Port D RealTime Input Data Register (PDRTIDR)
3QRI
The realtime input port stores the pin states of port D in PDRTIDR using the pin as the trigger input. The falling, rising, or both edges of the pin can be specified as a trigger timing by bits 7 and 6 in the IRQ sense control register L (ISCRL). For details of this setting, see section 5.3.3, IRQ Sense Control Registers H and L (ISCRH, ISCRL).
Bit 7 6 5 4 3 2 1 0 Bit Name PDRTIDR7 PDRTIDR6 PDRTIDR5 PDRTIDR4 PDRTIDR3 PDRTIDR2 PDRTIDR1 PDRTIDR0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description
3QRI
Stores pin states using the input.
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3QRI
pin as a trigger
Section 9 I/O Ports
9.10
Port F
Port F is an 8-bit I/O port that also has other functions. Port F has the following registers. * Port F data direction register (PFDDR) * Port F data register (PFDR) * Port F register (PORTF) 9.10.1 Port F Data Direction Register (PFDDR)
PFDDR is an 8-bit write-only register, the individual bits of which specify whether the pins of port F are used for input or output.
Bit 7 Bit Name PF7DDR Initial Value 0 R/W W Description When a pin is specified as a general purpose I/O port, setting this bit to 1 makes the PF7 pin a output pin. Clearing this bit to 0 makes the pin an input pin. When a pin is specified as a general purpose I/O port, setting these bits to 1 makes the corresponding port F pin an output pin. Clearing these bits to 0 makes the pin an input pin.
6 5 4 3 2 1 0
PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
0 0 0 0 0 0 0
W W W W W W W
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Section 9 I/O Ports
9.10.2
Port F Data Register (PFDR)
PFDR is an 8-bit readable/writable register that stores output data for the port F pins.
Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Output data for a pin is stored when the pin is specified as a general purpose I/O port.
9.10.3
Port F Register (PORTF)
PORTF is an 8-bit read-only register that shows port F pin states. PORTF cannot be modified.
Bit 7 6 5 4 3 2 1 0 Note: Bit Name PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 * Initial Value Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read.
Determined by the states of pins PF7 to PF0.
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Section 9 I/O Ports
9.10.4
Pin Functions
2QRI
Table 9.46 PF7 Pin Function
PF7DDR Pin function 0 PF7 input 1 output
Table 9.47 PF6 Pin Function
PF6DDR Pin function 0 PF6 input 1 PF6 output
Table 9.48 PF5 Pin Function
PF5DDR Pin function 0 PF5 input 1 PF5 output
Table 9.49 PF4 Pin Function
PF4DDR Pin function 0 PF4 input 1 PF4 output
Table 9.50 PF3 Pin Function
PF3DDR Pin function 0 PF3 input input*1 input*2
3QRI GRTDA
1 PF3 output
Notes: 1. input when TRGS0 = TRGS1 = 1. 2. When used as an external interrupt input pin, do not use as an I/O pin for another function. This pin also functions as the trigger input for the realtime input port.
GRTDA
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3QRI
Port F is an 8-bit I/O port. Port F pins also function as external interrupt input, A/D trigger input (ADTRG), and system clock output ().
and
,
Section 9 I/O Ports
Table 9.51 PF2 Pin Function
PF2DDR Pin function 0 PF2 input 1 PF2 output
Table 9.52 PF1 Pin Function
PF1DDR Pin function 0 PF1 input 1 PF1 output
Table 9.53 PF0 Pin Function
PF0DDR Pin function Note: * 0 PF0 input input*
2QRI
1 PF0 output
When used as an external interrupt input pin, do not use as an I/O pin for another function.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Section 10 16-Bit Timer Pulse Unit (TPU)
This LSI has an on-chip 16-bit timer pulse unit (TPU) comprised of six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively.
10.1
Features
* Maximum 16-pulse input/output * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation A maximum 15-phase PWM output is possible in combination with synchronous operation * Buffer operation settable for channels 0 and 3 * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 * Cascaded operation * Fast access via internal 16-bit bus * 26 interrupt sources * Automatic transfer of register data * Programmable pulse generator (PPG) output trigger can be generated * A/D converter conversion start trigger can be generated * Module stop mode can be set
TIMTPU0A_000020020300
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.1 TPU Functions
Item Count clock Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TGR compare match or input capture /1 /4 /16 /64 /256 TCLKA TCLKB TGRA_1 TGRB_1 TIOCA1 TIOCB1 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 TIOCA2 TIOCB2 /1 /4 /16 /64 /256 /1024 /4096 TCLKA TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture /1 /4 /16 /64 /1024 TCLKA TCLKC TGRA_4 TGRB_4 TIOCA4 TIOCB4 /1 /4 /16 /64 /256 TCLKA TCLKC TCLKD TGRA_5 TGRB_5 TIOCA5 TIOCB5
General registers (TGR) General registers/ buffer registers I/O pins
Counter clear function
TGR compare match or input capture
TGR compare match or input capture
TGR compare match or input capture
TGR compare match or input capture
Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation
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Section 10 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 TGR compare match or input capture TGRA_1 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture 4 sources Channel 2 TGR compare match or input capture TGRA_2 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture 4 sources Channel 3 TGR compare match or input capture TGRA_3 compare match or input capture Channel 4 TGR compare match or input capture TGRA_4 compare match or input capture Channel 5 TGR compare match or input capture TGRA_5 compare match or input capture
DTC TGR activation compare match or input capture A/D TGRA_0 converter compare trigger match or input capture PPG trigger TGRA_0/ TGRB_0 compare match or input capture 5 sources
TGRA_3/ TGRB_3 compare match or input capture 5 sources 4 sources
Interrupt sources
4 sources
* Compare * Compare * Compare * Compare * Compare * Compare match or match or match or match or match or match or input input input input input input capture 0A capture 1A capture 2A capture 3A capture 4A capture 5A * Compare * Compare * Compare * Compare * Compare * Compare match or match or match or match or match or match or input input input input input input capture 0B capture 1B capture 2B capture 3B capture 4B capture 5B * Overflow * Compare match or * Underflow input capture 0C * Compare match or input capture 0D * Overflow * Overflow * Underflow * Overflow * Compare match or * Underflow input capture 3C * Compare match or input capture 3D * Overflow * Overflow * Underflow
Legend: : Possible : Not possible
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Section 10 16-Bit Timer Pulse Unit (TPU)
TIORH TIORL
TMDR
Channel 3
TSR
TGRC
TGRD
TGRA
TGRB
TCNT
Input/output pins Channel 3:
TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5
Control logic for channels 3 to 5
TIOR
Channel 5:
TMDR
Channel 5
TSR
TIER
TCR
Channel 4:
TGRA
TIOR
Clock input Internal clock:
/1 /4 /16 /64 /256 /1024 /4096 TCLKA TCLKB TCLKC TCLKD
TIER
TCR
Module data bus
TSYR
TGRB
TCNT
Interrupt request signals Channel 3: TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 Channel 4: TGIA_4 TGIB_4 TCIV_4 TCIU_4 Channel 5: TGIA_5 TGIB_5 TCIV_5 TCIU_5
TMDR
Channel 4
TSR
TIER
TCR
TGRA
TGRB
TCNT
Control logic
Internal data bus
Common
Bus interface
External clock:
TSTR
A/D converter conversion start signal PPG output trigger signal
TMDR
Channel 2
TSR
TGRA
TIOR
Input/output pins Channel 0:
TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2
TIER
TCR
TGRB
TCNT
Channel 2:
TIORH TIORL
TMDR
Channel 0
TSR
TIER
TCR
Channel 1:
Interrupt request signals Channel 3: TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 Channel 4: TGIA_1 TGIB_1 TCIV_1 TCIU_1 Channel 5: TGIA_2 TGIB_2 TCIV_2 TCIU_2
TMDR
Control logic for channels 0 to 2
Channel 1
TSR
TGRA
TIOR
TGRB TGRC TGRD TGRB
TCNT TCNT
Legend: TSTR: Timer start register TSYR: Timer synchro register TCR: Timer control register TMDR: Timer mode register
TIOR (H, L): TIER: TSR: TGR (A, B, C, D):
Timer I/O control registers (H, L) Timer interrupt enable register Timer status register Timer general registers (A, B, C, D)
Figure 10.1 Block Diagram of TPU
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TIER
TCR
TGRA
Section 10 16-Bit Timer Pulse Unit (TPU)
10.2
Input/Output Pins
Table 10.2 TPU Pins
Channel All Symbol TCLKA TCLKB TCLKC TCLKD 0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 1 TIOCA1 TIOCB1 2 TIOCA2 TIOCB2 3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 4 TIOCA4 TIOCB4 5 TIOCA5 TIOCB5 I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function External clock A input pin (Channel 1 and 5 phase counting mode A phase input) External clock B input pin (Channel 1 and 5 phase counting mode B phase input) External clock C input pin (Channel 2 and 4 phase counting mode A phase input) External clock D input pin (Channel 2 and 4 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRA_5 input capture input/output compare output/PWM output pin TGRB_5 input capture input/output compare output/PWM output pin
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3
Register Descriptions
The TPU has the following registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Timer control register_0 (TCR_0) Timer mode register_0 (TMDR_0) Timer I/O control register H_0 (TIORH_0) Timer I/O control register L_0 (TIORL_0) Timer interrupt enable register_0 (TIER_0) Timer status register_0 (TSR_0) Timer counter_0 (TCNT_0) Timer general register A_0 (TGRA_0) Timer general register B_0 (TGRB_0) Timer general register C_0 (TGRC_0) Timer general register D_0 (TGRD_0) Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register _1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1) Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2) Timer control register_3 (TCR_3) Timer mode register_3 (TMDR_3) Timer I/O control register H_3 (TIORH_3)
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Section 10 16-Bit Timer Pulse Unit (TPU)
* * * * * * * * * * * * * * * * * * * * * * * *
Timer I/O control register L_3 (TIORL_3) Timer interrupt enable register_3 (TIER_3) Timer status register_3 (TSR_3) Timer counter_3 (TCNT_3) Timer general register A_3 (TGRA_3) Timer general register B_3 (TGRB_3) Timer general register C_3 (TGRC_3) Timer general register D_3 (TGRD_3) Timer control register_4 (TCR_4) Timer mode register_4 (TMDR_4) Timer I/O control register _4 (TIOR_4) Timer interrupt enable register_4 (TIER_4) Timer status register_4 (TSR_4) Timer counter_4 (TCNT_4) Timer general register A_4 (TGRA_4) Timer general register B_4 (TGRB_4) Timer control register_5 (TCR_5) Timer mode register_5 (TMDR_5) Timer I/O control register_5 (TIOR_5) Timer interrupt enable register_5 (TIER_5) Timer status register_5 (TSR_5) Timer counter_5 (TCNT_5) Timer general register A_5 (TGRA_5) Timer general register B_5 (TGRB_5)
Common Registers * Timer start register (TSTR) * Timer synchro register (TSYR)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.1
Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel (channels 5 to 0). TCR register settings should be conducted only when TCNT operation is stopped.
Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 10.3 and 10.4 for details. Clock Edge 1 and 0 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges Legend: x: Don't care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 10.5 to 10.10 for details.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3)
Channel 0, 3 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture*2 TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1
1
0
0 1
1
0 1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Channel 1, 2, 4, 5 Bit 7 Bit 6 Reserved*2 CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation*
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.5 TPSC2 to TPSC0 (Channel 0)
Channel 0 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input
Table 10.6 TPSC2 to TPSC0 (Channel 1)
Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Counts on TCNT2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase counting mode.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.7 TPSC2 to TPSC0 (Channel 2)
Channel 2 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 10.8 TPSC2 to TPSC0 (Channel 3)
Channel 3 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input Internal clock: counts on /1024 Internal clock: counts on /256 Internal clock: counts on /4096
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.9 TPSC2 to TPSC0 (Channel 4)
Channel 4 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Counts on TCNT5 overflow/underflow
Note: This setting is ignored when channel 4 is in phase counting mode.
Table 10.10 TPSC2 to TPSC0 (Channel 5)
Channel 5 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /256 External clock: counts on TCLKD pin input
Note: This setting is ignored when channel 5 is in phase counting mode.
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.2
Timer Mode Register (TMDR)
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be changed only when TCNT operation is stopped.
Bit 7, 6 Bit Name Initial value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 3 to 0 These bits are used to set the timer operating mode. MD3 is a reserved bit. In a write, it should always be written with 0. See table 10.11 for details.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.11 MD3 to MD0
Bit 3 MD3*1 0 Bit 2 MD2*2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 x x 0 1 1 x Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4
Legend: x: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.3
Timer I/O Control Register (TIOR)
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. * TIORH_5, TIOR_4, TIOR_3, TIORH_2, TIOR_1, TIOR_0
Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description I/O Control B3 to B0 Specify the function of TGRB.
I/O Control A3 to A0 Specify the function of TGRA.
* TIORL_3, TIORL_0
Bit 7 6 5 4 3 2 1 0 Bit Name IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description I/O Control D3 to D0 Specify the function of TGRD.
I/O Control C3 to C0 Specify the function of TGRC.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.12 TIORH_0 (Channel 0)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_0 Function Output compare register TIOCB0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCB0 pin Input capture at rising edge Capture input source is the TIOCB0 pin Input capture at falling edge Capture input source is the TIOCB0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down*
Legend: x: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.13 TIORL_0 (Channel 0)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register*2 TGRD_0 Function Output compare register*2 TIOCD0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCD0 pin Input capture at rising edge Capture input source is the TIOCD0 pin Input capture at falling edge Capture input source is the TIOCD0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down*1 Legend: x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.14 TIOR_1 (Channel 1)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCB1 pin Input capture at rising edge Capture input source is the TIOCB1 pin Input capture at falling edge Capture input source is the TIOCB1 pin Input capture at both edges TGRC_0 compare match/ input capture Input capture at generation of TGRC_0 compare match/input capture Legend: x: Don't care
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.15 TIOR_2 (Channel 2)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don't care x Input capture register TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCB2 pin Input capture at rising edge Capture input source is the TIOCB2 pin Input capture at falling edge Capture input source is the TIOCB2 pin Input capture at both edges
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.16 TIORH_3 (Channel 3)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_3 Function Output compare register TIOCB3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCB3 pin Input capture at rising edge Capture input source is the TIOCB3 pin Input capture at falling edge Capture input source is the TIOCB3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* Legend: x: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.17 TIORL_3 (Channel 3)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register*2 TGRD_3 Function Output compare register*2 TIOCD3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCD3 pin Input capture at rising edge Capture input source is the TIOCD3 pin Input capture at falling edge Capture input source is the TIOCD3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down*1 Legend: x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.18 TIOR_4 (Channel 4)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_4 Function Output compare register TIOCB4 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCB4 pin Input capture at rising edge Capture input source is the TIOCB4 pin Input capture at falling edge Capture input source is the TIOCB4 pin Input capture at both edges Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture Legend: x: Don't care
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Table 10.19 TIOR_5 (Channel 5)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don't care x Input capture register TGRB_5 Function Output compare register TIOCB5 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCB5 pin Input capture at rising edge Capture input source is the TIOCB5 pin Input capture at falling edge Capture input source is the TIOCB5 pin Input capture at both edges
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.20 TIORH_0 (Channel 0)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 Legend: x: Don't care x x x Input capture register TGRA_0 Function Output compare register TIOCA0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCA0 pin Input capture at rising edge Capture input source is the TIOCA0 pin Input capture at falling edge Capture input source is the TIOCA0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.21 TIORL_0 (Channel 0)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register* TGRC_0 Function Output compare register* TIOCC0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCC0 pin Input capture at rising edge Capture input source is the TIOCC0 pin Input capture at falling edge Capture input source is the TIOCC0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: x: Don't care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.22 TIOR_1 (Channel 1)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCA1 pin Input capture at rising edge Capture input source is the TIOCA1 pin Input capture at falling edge Capture input source is the TIOCA1 pin Input capture at both edges Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture Legend: x: Don't care
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.23 TIOR_2 (Channel 2)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don't care x Input capture register TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCA2 pin Input capture at rising edge Capture input source is the TIOCA2 pin Input capture at falling edge Capture input source is the TIOCA2 pin Input capture at both edges
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.24 TIORH_3 (Channel 3)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 Legend: x: Don't care x x x Input capture register TGRA_3 Function Output compare register TIOCA3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCA3 pin Input capture at rising edge Capture input source is the TIOCA3 pin Input capture at falling edge Capture input source is the TIOCA3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.25 TIORL_3 (Channel 3)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register* TGRC_3 Function Output compare register* TIOCC3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCC3 pin Input capture at rising edge Capture input source is the TIOCC3 pin Input capture at falling edge Capture input source is the TIOCC3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down Legend: x: Don't care Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.26 TIOR_4 (Channel 4)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_4 Function Output compare register TIOCA4 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCA4 pin Input capture at rising edge Capture input source is the TIOCA4 pin Input capture at falling edge Capture input source is the TIOCA4 pin Input capture at both edges Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture Legend: x: Don't care
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.27 TIOR_5 (Channel 5)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don't care x Input capture register TGRA_5 Function Output compare register TIOCA5 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is the TIOCA5 pin Input capture at rising edge Capture input source is the TIOCA5 pin Input capture at falling edge Capture input source is the TIOCA5 pin Input capture at both edges
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.4
Timer Interrupt Enable Register (TIER)
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel.
Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 5
TCIEU
1 0
R/W
Reserved This bit is always read as 1 and cannot be modified. Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled
4
TCIEV
0
R/W
Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled
3
TGIED
0
R/W
TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled
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Section 10 16-Bit Timer Pulse Unit (TPU) Bit 2 Bit Name TGIEC Initial value 0 R/W R/W Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.5
Timer Status Register (TSR)
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel.
Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 5
TCFU
1 0
R/(W)
Reserved This bit is always read as 1 and cannot be modified. Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] * When the TCNT value underflows (changes from H'0000 to H'FFFF) When 0 is written to TCFU after reading TCFU = 1
[Clearing condition] * 4 TCFV 0 R/(W)
Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition] * When the TCNT value overflows (changes from H'FFFF to H'0000 ) When 0 is written to TCFV after reading TCFV = 1
[Clearing condition] *
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Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit Name TGFD Initial value 0 R/W R/(W) Description Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. Only 0 can be written, for flag clearing. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRD and TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register When DTC is activated by TGID interrupt and the DISEL bit of MRB in DTC is 0 When 0 is written to TGFD after reading TGFD = 1
[Clearing conditions] * * 2 TGFC 0 R/(W)
Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. Only 0 can be written, for flag clearing. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register When DTC is activated by TGIC interrupt and the DISEL bit of MRB in DTC is 0 When 0 is written to TGFC after reading TGFC = 1
[Clearing conditions] * *
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Section 10 16-Bit Timer Pulse Unit (TPU) Bit 1 Bit Name TGFB Initial value 0 R/W R/(W) Description Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRB and TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register When DTC is activated by TGIB interrupt and the DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB = 1
[Clearing conditions] * * 0 TGFA 0 R/(W)
Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register When DTC is activated by TGIA interrupt and the DISEL bit of MRB in DTC is 0 When 0 is written to TGFA after reading TGFA = 1
[Clearing conditions] * *
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.6
Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 10.3.7 Timer General Register (TGR)
The TGR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA- TGRC and TGRB-TGRD. 10.3.8 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Bit 7, 6 5 4 3 2 1 0 Bit Name Initial value All 0 0 0 0 0 0 0 R/W Description Reserved The write value should always be 0. CST5 CST4 CST3 CST2 CST1 CST0 R/W R/W R/W R/W R/W R/W Counter Start 5 to 0 (CST5 to CST0) These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped 1: TCNT_5 to TCNT_0 performs count operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.9
Timer Synchro Register (TSYR)
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit 7, 6 5 4 3 2 1 0 Bit Name Initial value All 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Timer Synchro 0 to 5 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_0 to TCNT_5 operates independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_0 to TCNT_5 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4
10.4.1
Operation
Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST5 to CST0 is set to 1 in TSTR, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. 1. Example of count operation setting procedure Figure 10.2 shows an example of the count operation setting procedure.
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation.
Operation selection
Select counter clock
[1]
Periodic counter
Free-running counter
Select counter clearing source
[2]
[3] Select output compare register
Set period
[4]
Start count operation
[5]
Start count operation
Figure 10.2 Example of Counter Operation Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
2. Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10.3 illustrates free-running counter operation.
TCNT value H'FFFF
H'0000
Time
CST bit
TCFV
Figure 10.3 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 10.4 illustrates periodic counter operation.
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Section 10 16-Bit Timer Pulse Unit (TPU)
TCNT value TGR
Counter cleared by TGR compare match
H'0000
Time
CST bit Flag cleared by software or DTC activation TGF
Figure 10.4 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. Example of setting procedure for waveform output by compare match Figure 10.5 shows an example of the setting procedure for waveform output by compare match.
[1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin unit the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation.
Output selection
Select waveform output mode
[1]
Set output timing
[2]
Start count operation
[3]

Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match
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2. Examples of waveform output operation Figure 10.6 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time
Figure 10.6 Example of 0 Output/1 Output Operation Figure 10.7 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output
TIOCB TIOCA
Figure 10.7 Example of Toggle Output Operation
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Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, /1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if /1 is selected. 1. Example of input capture operation setting procedure Figure 10.8 shows an example of the input capture operation setting procedure.
[1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. [1]
Input selection
Select input capture input
Start count
[2]

Figure 10.8 Example of Input Capture Operation Setting Procedure
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2. Example of input capture operation Figure 10.9 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB input (falling edge)
TCNT value H'0180 H'0160
H'0010 H'0005 H'0000 Time
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB TGRB H'0180
Figure 10.9 Example of Input Capture Operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.2
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 10.10 shows an example of the synchronous operation setting procedure.
Synchronous operation selection Set synchronous operation [1]
Synchronous presetting
Synchronous clearing
Set TCNT
[2]
Clearing source generation channel? Yes Select counter clearing source Start count
No
[3]
Set synchronous counter clearing Start count
[4]
[4]
[5]

[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 10.10 Example of Synchronous Operation Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation: Figure 10.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing sources. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 10.4.5, PWM Modes.
Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time
TIOCA_0 TIOCA_1 TIOCA_2
Figure 10.11 Example of Synchronous Operation 10.4.3 Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10.28 shows the register combinations used in buffer operation.
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Table 10.28 Register Combinations in Buffer Operation
Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3
* When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.12.
Compare match signal
Buffer register
Timer general register
Comparator
TCNT
Figure 10.12 Compare Match Buffer Operation * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10.13.
Input capture signal
Buffer register
Timer general register
TCNT
Figure 10.13 Input Capture Buffer Operation
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Example of Buffer Operation Setting Procedure: Figure 10.14 shows an example of the buffer operation setting procedure.
Buffer operation
Select TGR function
[1]
[1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation.
Set buffer operation
[2]
Start count
[3]

Figure 10.14 Example of Buffer Operation Setting Procedure
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Examples of Buffer Operation: 1. When TGR is an output compare register Figure 10.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 10.4.5, PWM Modes.
TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520
H'0450
TIOCA
Figure 10.15 Example of Buffer Operation (1)
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Section 10 16-Bit Timer Pulse Unit (TPU)
2. When TGR is an input capture register Figure 10.16 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value H'0F07 H'09FB H'0532 H'0000 Time
TIOCA
TGRA
H'0532
H'0F07
H'09FB
TGRC
H'0532
H'0F07
Figure 10.16 Example of Buffer Operation (2)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.4
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10.29 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 10.29 Cascaded Combinations
Combination Channels 1 and 2 Channels 4 and 5 Upper 16 Bits TCNT_1 TCNT_4 Lower 16 Bits TCNT_2 TCNT_5
Example of Cascaded Operation Setting Procedure: Figure 10.17 shows an example of the setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
[1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'111 to select TCNT_2 (TCNT_5) overflow/underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation.
Start count
[2]

Figure 10.17 Cascaded Operation Setting Procedure
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Examples of Cascaded Operation: Figure 10.18 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1, when TGRA_1 and TGRA_2 have been designated as input capture registers, and when TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
TCNT_1 clock TCNT_1 TCNT_2 clock TCNT_2 TIOCA2, TIOCA1 TGRA_1 H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2
TGRA_2
H'0000
Figure 10.18 Example of Cascaded Operation (1) Figure 10.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKA
TCLKB TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF
TCNT_1
0000
0001
0000
Figure 10.19 Example of Cascaded Operation (2)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a duty cycle register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10.30.
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Table 10.30 PWM Output Registers and Output Pins
Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGR4A_4 TGR4B_4 5 Note: TGRA_5 TGRB_5 * TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5
In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Example of PWM Mode Setting Procedure: Figure 10.20 shows an example of the PWM mode setting procedure.
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PWM mode
Select counter clock
[1]
Select counter clearing source
[2]
Select waveform output level
[3]
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 start the count operation.
Set TGR
[4]
Set PWM mode
[5]
Start count
[6]

Figure 10.20 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 10.21 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty cycle levels.
TCNT value TGRA
Counter cleared by TGRA compare match
TGRB H'0000 Time
TIOCA
Figure 10.21 Example of PWM Mode Operation (1)
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Figure 10.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty cycle levels.
Counter cleared by TGRB_1 compare match
TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000
Time TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 10.22 Example of PWM Mode Operation (2)
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Figure 10.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode.
TCNT value TGRB rewritten TGRA
TGRB H'0000
TGRB rewritten
TGRB rewritten Time
TIOCA
0% duty
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time
TIOCA
Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten
TGRB H'0000 100% duty 0% duty
TGRB rewritten Time
TIOCA
Figure 10.23 Example of PWM Mode Operation (3)
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 10.31 shows the correspondence between external clock pins and channels. Table 10.31 Phase Counting Mode Clock Input Pins
External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 10.24 shows an example of the phase counting mode setting procedure.
Phase counting mode
[1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. [1]
Select phase counting mode
Start count
[2]

Figure 10.24 Example of Phase Counting Mode Setting Procedure
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Section 10 16-Bit Timer Pulse Unit (TPU)
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 10.25 shows an example of phase counting mode 1 operation, and table 10.32 summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value
Up-count
Down-count
Time
Figure 10.25 Example of Phase Counting Mode 1 Operation Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count
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Section 10 16-Bit Timer Pulse Unit (TPU)
2. Phase counting mode 2 Figure 10.26 shows an example of phase counting mode 2 operation, and table 10.33 summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count
Time
Figure 10.26 Example of Phase Counting Mode 2 Operation Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count
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Section 10 16-Bit Timer Pulse Unit (TPU)
3. Phase counting mode 3 Figure 10.27 shows an example of phase counting mode 3 operation, and table 10.34 summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value
Up-count
Down-count
Time
Figure 10.27 Example of Phase Counting Mode 3 Operation Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care
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Section 10 16-Bit Timer Pulse Unit (TPU)
4. Phase counting mode 4 Figure 10.28 shows an example of phase counting mode 4 operation, and table 10.35 summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value
Up-count
Down-count
Time
Figure 10.28 Example of Phase Counting Mode 4 Operation Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count
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Section 10 16-Bit Timer Pulse Unit (TPU)
Phase Counting Mode Application Example: Figure 10.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed.
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Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1
TGRA_1 (speed period capture) TGRB_1 (speed period capture)
TCNT_0 + + -
TGRA_0 (speed control period) TGRC_0 (position control period)
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation) Channel 0
Figure 10.29 Phase Counting Mode Application Example
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.5
Interrupt Sources
There are three kinds of TPU interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 10.36 lists the TPU interrupt sources.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.36 TPU Interrupts
Channel 0 Name TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 1 TGIA_1 TGIB_1 TCIV_1 TCIU_1 2 TGIA_2 TGIB_2 TCIV_2 TCIU_2 3 TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 4 TGIA_4 TGIB_4 TCIV_4 TCIU_4 5 TGIA_5 TGIB_5 TCIV_5 TCIU_5 Note: * Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TCNT_4 overflow TCNT_4 underflow TGRA_5 input capture/compare match TGRB_5 input capture/compare match TCNT_5 overflow TCNT_5 underflow DTC Interrupt Flag Activation TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TCFV_4 TCFU_4 TGFA_5 TGFB_5 TCFV_5 TCFU_5 Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible
This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.
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Section 10 16-Bit Timer Pulse Unit (TPU)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5.
10.6
DTC Activation
The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 8, Data Transfer Controller (DTC). A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
10.7
A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to begin A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is begun. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel.
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.8
10.8.1
Operation Timing
Input/Output Timing
TCNT Count Timing: Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation.
Internal clock
Falling edge
Rising edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 10.30 Count Timing in Internal Clock Operation
External clock
Falling edge
Rising edge
Falling edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 10.31 Count Timing in External Clock Operation
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Section 10 16-Bit Timer Pulse Unit (TPU)
Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.32 shows output compare output timing.
TCNT input clock N N+1
TCNT
TGR
N
Compare match signal TIOC pin
Figure 10.32 Output Compare Output Timing Input Capture Signal Timing: Figure 10.33 shows input capture signal timing.
Input capture input Input capture signal
TCNT
N
N+1
N+2
TGR
N
N+2
Figure 10.33 Input Capture Input Signal Timing
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Section 10 16-Bit Timer Pulse Unit (TPU)
Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.34 shows the timing when counter clearing on compare match is specified, and figure 10.35 shows the timing when counter clearing on input capture is specified.
Compare match signal Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 10.34 Counter Clear Timing (Compare Match)
Input capture signal
Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 10.35 Counter Clear Timing (Input Capture)
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Section 10 16-Bit Timer Pulse Unit (TPU)
Buffer Operation Timing: Figures 10.36 and 10.37 show the timing in buffer operation.
TCNT
n
n+1
Compare match signal TGRA, TGRB TGRC, TGRD
n
N
N
Figure 10.36 Buffer Operation Timing (Compare Match)
Input capture signal
TCNT
N
N+1
TGRA, TGRB TGRC, TGRD
n
N
N+1
n
N
Figure 10.37 Buffer Operation Timing (Input Capture) 10.8.2 Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 10.38 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing.
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Section 10 16-Bit Timer Pulse Unit (TPU)
TCNT input clock
TCNT
N
N+1
TGR
N
Compare match signal
TGF flag
TGI interrupt
Figure 10.38 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 10.39 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing.
Input capture signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 10.39 TGI Interrupt Timing (Input Capture)
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Section 10 16-Bit Timer Pulse Unit (TPU)
TCFV Flag/TCFU Flag Setting Timing: Figure 10.40 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing.
TCNT input clock TCNT (overflow) Overflow signal
H'FFFF
H'0000
TCFV flag
TCIV interrupt
Figure 10.40 TCIV Interrupt Setting Timing
TCNT input clock TCNT (underflow) Underflow signal
H'0000
H'FFFF
TCFU flag
TCIU interrupt
Figure 10.41 TCIU Interrupt Setting Timing
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Section 10 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.42 shows the timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag clearing by the DTC.
TSR write cycle T2 T1
Address
TSR address
Write signal
Status flag
Interrupt request signal
Figure 10.42 Timing for Status Flag Clearing by CPU
DTC read cycle T1 T2 DTC write cycle T1 T2
Address
Source address
Destination address
Status flag
Interrupt request signal
Figure 10.43 Timing for Status Flag Clearing by DTC Activation
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9
10.9.1
Usage Notes
Module Stop Mode Setting
TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes. 10.9.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.44 shows the input clock conditions in phase counting mode.
Phase Phase differdifferOverlap ence ence
Overlap TCLKA (TCLKC) TCLKB (TCLKD)
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.3
Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where (N + 1) f : Counter frequency : Operating frequency N : TGR set value Conflict between TCNT Write and Clear Operations
10.9.4
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.45 shows the timing in this case.
TCNT write cycle T2 T1
Address
TCNT address
Write signal Counter clear signal
TCNT
N
H'0000
Figure 10.45 Conflict between TCNT Write and Clear Operations
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.5
Conflict between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.46 shows the timing in this case.
TCNT write cycle T2 T1
Address
TCNT address
Write signal TCNT input clock N TCNT write data M
TCNT
Figure 10.46 Conflict between TCNT Write and Increment Operations
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.6
Conflict between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the previous value is written. Figure 10.47 shows the timing in this case.
TGR write cycle T2 T1 Address TGR address
Write signal Compare match signal TCNT N N+1
Prohibited
TGR
N TGR write data
M
Figure 10.47 Conflict between TGR Write and Compare Match
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.7
Conflict between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation will be that in the buffer prior to the write. Figure 10.48 shows the timing in this case.
TGR write cycle T1 T2 Address Buffer register address
Write signal Compare match signal Buffer register write data Buffer register TGR N M
N
Figure 10.48 Conflict between Buffer Register Write and Compare Match
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.8
Conflict between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 10.49 shows the timing in this case.
TGR read cycle T1 T2 Address TGR address
Read signal Input capture signal TGR X M
Internal data bus
M
Figure 10.49 Conflict between TGR Read and Input Capture
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.9
Conflict between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.50 shows the timing in this case.
TGR write cycle T1 T2 Address TGR address
Write signal Input capture signal TCNT M
TGR
M
Figure 10.50 Conflict between TGR Write and Input Capture
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.10 Conflict between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.51 shows the timing in this case.
Buffer register write cycle T1 T2 Address Buffer register address
Write signal Input capture signal TCNT N
TGR Buffer register
M
N
M
Figure 10.51 Conflict between Buffer Register Write and Input Capture
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.11 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.52 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR.
TCNT input clock TCNT Counter clear signal TGF Prohibited TCFV H'FFFF H'0000
Figure 10.52 Conflict between Overflow and Counter Clearing
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.12 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.53 shows the operation timing when there is conflict between TCNT write and overflow.
TCNT write cycle T2 T1
Address
TCNT address
Write signal
TCNT write data H'FFFF Prohibited M
TCNT
TCFV flag
Figure 10.53 Conflict between TCNT Write and Overflow 10.9.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 10.9.14 Interrupts in Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode.
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Section 11 8-Bit Timers
Section 11 8-Bit Timers
This LSI has an on-chip 8-bit timer module with four channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
11.1
Features
* Selection of clock sources Selected from three internal clocks (/8, /64, and /8192) and an external clock. * Selection of three ways to clear the counters The counters can be cleared on compare-match A or B, or by an external reset signal. * Timer output controlled by two compare-match signals The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or PWM output with an arbitrary duty cycle. * Cascading of the two channels Cascading of TMR_1 and TMR_0 The module can operate as a 16-bit timer using TMR_0 as the upper half and TMR_1 as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count mode). Cascading of TMR_3 and TMR_2 The module can operate as a 16-bit timer using TMR_2 as the upper half and TMR_3 as the lower half (16-bit count mode). TMR_3 can be used to count TMR_2 compare-match occurrences (compare-match count mode). * Multiple interrupt sources for each channel Two compare-match interrupts and one overflow interrupt can be requested independently. * Generation of A/D conversion start trigger Channel 0 compare-match A signal can be used as the A/D conversion start trigger. * Module stop mode can be set At initialization, the 8-bit timer operation is halted. Register access is enabled by canceling the module stop mode.
TIMH263A_000020020300
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Section 11 8-Bit Timers
Figure 11.1 shows a block diagram of the 8-bit timer module (TMR_1 and TMR_0).
External clock sources TMCI01 Internal clock sources /8 /64 /8192
Clock 1 Clock 0 Clock select TCORA_0 Compare-match A1 Compare-match A0 Comparator A_0 Overflow 1 Overflow 0 Clear 0 Clear 1 Compare-match B1 Compare-match B0 Comparator B_0 TMO1 Control logic TCORB_0 TCORB_1 Comparator B_1 TCORA_1
Comparator A_1
TMO0 TMRI01
TCNT_0
TCNT_1
TCSR_0 A/D conversion start request signal TCR_0 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals
TCSR_1
TCR_1
Legend:
TCORA_0: TCORB_0: TCNT_0: TCSR_0: TCR_0: Time constant register A_0 Time constant register B_0 Timer counter_0 Timer control/status register_0 Timer control register_0 TCORA_1: TCORB_1: TCNT_1: TCSR_1: TCR_1: Time constant register A_1 Time constant register B_1 Timer counter_1 Timer control/status register_1 Timer control register_1
Figure 11.1 Block Diagram of 8-Bit Timer Module
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Internal bus
Section 11 8-Bit Timers
11.2
Input/Output Pins
Table 11.1 summarizes the input and output pins of the 8-bit timer module. Table 11.1 Pin Configuration
Channel 0 1 Common to 0 and 1 2 3 Common to 2 and 3 Name Timer output Timer output Timer clock input Timer reset input Timer output Timer output Timer clock input Timer reset input Symbol TMO0 TMO1 TMCI01 TMRI01 TMO2 TMO3 TMCI23 TMRI23 I/O Output Output Input Input Output Output Input Input Function Output controlled by compare-match Output controlled by compare-match External clock input for the counter External reset input for the counter Output controlled by compare-match Output controlled by compare-match External clock input for the counter External reset input for the counter
11.3
Register Descriptions
The 8-bit timer has the following registers. For details on the module stop register, refer to 21.1.2, Module Stop Registers A to C (MSTPCRA to MSTPCRC). * * * * * * * * * * * * * * * * Timer counter_0 (TCNT_0) Time constant register A_0 (TCORA_0) Time constant register B_0 (TCORB_0) Timer control register_0 (TCR_0) Timer control/status register_0 (TCSR_0) Timer counter_1 (TCNT_1) Time constant register A_1 (TCORA_1) Time constant register B_1 (TCORB_1) Timer control register_1 (TCR_1) Timer control/status register_1 (TCSR_1) Timer counter_2 (TCNT_2) Time constant register A_2 (TCORA_2) Time constant register B_2 (TCORB_2) Timer control register_2 (TCR_2) Timer control/status register_2 (TCSR_2) Timer counter_3 (TCNT_3)
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Section 11 8-Bit Timers
* * * *
Time constant register A_3 (TCORA_3) Time constant register B_3 (TCORB_3) Timer control register_3 (TCR_3) Timer control/status register_3 (TCSR_3) Timer Counters (TCNT)
11.3.1
Each TCNT is an 8-bit up-counter. TCNT_1 and TCNT_0, or TCNT_3 and TCNT_2 comprise a single 16-bit register, so they can be accessed together by word access. This clock source is selected by clock select bits CKS2 to CKS0 in TCR. TCNT can be cleared by an external reset input signal or compare-match signals A and B. Counter clear bits CCLR1 and CCLR0 in TCR select the method of clearing. When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in TCSR is set to 1. The initial value of TCNT is H'00. 11.3.2 Time Constant Registers A (TCORA)
TCORA is an 8-bit readable/writable register. TCORA_3, TCORA_2, TCORA_1 and TCORA_0 comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by the compare-match signal A and the settings of output select bits OS1 and OS0 in TCSR. The initial value of TCORA is H'FF. 11.3.3 Time Constant Registers B (TCORB)
TCORB is an 8-bit readable/writable register. TCORB_3, TCORB_2, TCORB_1 and TCORB_0 comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set. Note, however, that comparison is disabled during the T2 state of a TCORB write cycle.
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Section 11 8-Bit Timers
The timer output from the TMO pin can be freely controlled by the compare-match signal B and the settings of output select bits OS1 and OS0 in TCSR. The initial value of TCORB is H'FF. 11.3.4 Timer Control Registers (TCR)
TCR selects the TCNT clock source and the time at which TCNT is cleared, and controls interrupt requests.
Bit 7 Bit Name CMIEB Initial Value 0 R/W R/W Description Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt request (CMIB) is disabled 1: CMFB interrupt request (CMIB) is enabled 6 CMIEA 0 R/W Compare-Match Interrupt Enable A Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt request (CMIA) is disabled 1: CMFA interrupt request (CMIA) is enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt request (OVI) is disabled 1: OVF interrupt request (OVI) is enabled 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1 and 0 These bits select the method by which TCNT is cleared 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input
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Section 11 8-Bit Timers Initial Value 0 0 0
Bit 2 1 0
Bit Name CKS2 CKS1 CKS0
R/W R/W R/W R/W
Description Clock Select 2 to 0 The input clock can be selected from three clocks divided from the system clock (). When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. 000: Clock input disabled 001: /8 internal clock source, counted on the falling edge 010: /64 internal clock source, counted on the falling edge 011: /8192 internal clock source, counted on the falling edge 100: For channel 0: Counted on TCNT1 overflow signal* For channel 1: Counted on TCNT0 overflow signal* For channel 2: Counted on TCNT3 overflow signal* For channel 3: Counted on TCNT2 overflow signal* 101: External clock source, counted at rising edge 110: External clock source, counted at falling edge 111: External clock source, counted at both rising and falling edges
Note:
*
If the count input of channel 0 (channel 2) is the TCNT1 (TCNT3) overflow signal and that of channel 1 (channel 3) is the TCNT1 (TCNT3) compare-match signal, no incrementing clock will be generated. Do not use this setting.
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Section 11 8-Bit Timers
11.3.5
Timer Control/Status Registers (TCSR)
TCSR indicates status flags and controls compare-match output. * TCSR_0
Bit 7 Bit Name CMFB Initial Value 0 R/W R/(W)* Description Compare-Match Flag B [Setting condition] * * * 6 CMFA 0 R/(W)* When TCNT = TCORB Read CMFB when CMFB = 1, then write 0 in CMFB. DTC is activated by the CMIB interrupt and the DISEL bit = 0 in MRB of TDC. [Clearing conditions]
Compare-match Flag A [Setting condition] * * * When TCNT = TCORA Read CMFA when CMFA = 1, then write 0 in CMFA. DTC is activated by the CMIA interrupt and DISEL bit = 0 in MRB of DTC. [Clearing conditions]
5
OVF
0
R/(W)*
Timer Overflow Flag [Setting condition] * * When TCNT overflows from H'FF to H'00 Read OVF when OVF = 1, then write 0 in OVF [Clearing condition]
4
ADTE
0
R/W
A/D Trigger Enable Enables or disables A/D converter start requests by compare-match A. 0: A/D converter start requests by compare-match A are disabled 1: A/D converter start requests by compare-match A are enabled
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Section 11 8-Bit Timers Initial Value 0 0
Bit 3 2
Bit Name OS3 OS2
R/W R/W R/W
Description Output Select 3 and 2 These bits specify how the timer output level is to be changed by a compare-match B of TCORB and TCNT. 00: No change when compare-match B occurs 01: 0 is output when compare-match B occurs 10: 1 is output when compare-match B occurs 11: Output is inverted when compare-match B occurs (toggle output)
1 0
OS1 OS0
0 0
R/W R/W
Output Select 1 and 0 These bits specify how the timer output level is to be changed by a compare-match A of TCORA and TCNT. 00: No change when compare-match A occurs 01: 0 is output when compare-match A occurs 10: 1 is output when compare-match A occurs 11: Output is inverted when compare-match A occurs (toggle output)
Note:
*
Only a 0 can be written to this bit, to clear the flag
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Section 11 8-Bit Timers
* TCSR_3 and TCSR_1
Bit 7 Bit Name CMFB Initial Value 0 R/W R/(W)* Description Compare-Match Flag B [Setting condition] * * * 6 CMFA 0 R/(W)* When TCNT = TCORB Read CMFB when CMFB = 1, then write 0 in CMFB DTC is activated by the CMIB interrupt and the DISEL bit = 0 in MRB of DTC. [Clearing conditions]
Compare-match Flag A [Setting condition] * * * When TCNT = TCORA Read CMFA when CMFA = 1, then write 0 in CMFA DTC is activated by the CMIA interrupt and the DISEL bit = 0 in MRB of DTC. [Clearing conditions]
5
OVF
0
R/(W)*
Timer Overflow Flag [Setting condition] * * When TCNT overflows from H'FF to H'00 Read OVF when OVF = 1, then write 0 in OVF [Clearing condition]
4 3 2
OS3 OS2
1 0 0
R/W R/W
Reserved This bit is always read as 1 and cannot be modified. Output Select 3 and 2 These bits specify how the timer output level is to be changed by a compare-match B of TCORB and TCNT. 00: No change when compare-match B occurs 01: 0 is output when compare-match B occurs 10: 1 is output when compare-match B occurs 11: Output is inverted when compare-match B occurs (toggle output)
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Section 11 8-Bit Timers Initial Value 0 0
Bit 1 0
Bit Name OS1 OS0
R/W R/W R/W
Description Output Select 1 and 0 These bits specify how the timer output level is to be changed by a compare-match A of TCORA and TCNT. 00: No change when compare-match A occurs 01: 0 is output when compare-match A occurs 10: 1 is output when compare-match A occurs 11: Output is inverted when compare-match A occurs (toggle output)
Note:
*
Only a 0 can be written to this bit, to clear the flag.
* TCSR_2
Bit 7 Bit Name CMFB Initial Value 0 R/W R/(W)* Description Compare-Match Flag B [Setting condition] * * * 6 CMFA 0 R/(W)* When TCNT = TCORB Read CMFB when CMFB = 1, then write 0 in CMFB DTC is activated by the CMIB interrupt and the DISEL bit = 0 in MRB of DTC. [Clearing conditions]
Compare-match Flag A [Setting condition] When TCNT = TCORA [Clearing conditions] * * Read CMFA when CMFA = 1, then write 0 in CMFA DTC is activated by the CMIA interrupt and the DISEL bit = 0 in MRB of DTC.
5
OVF
0
R/(W)*
Timer Overflow Flag [Setting condition] * * When TCNT overflows from H'FF to H'00 Read OVF when OVF = 1, then write 0 in OVF [Clearing condition]
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Section 11 8-Bit Timers Initial Value 0
Bit 4
Bit Name
R/W R/W
Description Reserved This bit is a readable/writable bit, but the write value should always be 0.
3 2
OS3 OS2
0 0
R/W R/W
Output Select 3 and 2 These bits specify how the timer output level is to be changed by a compare-match B of TCORB and TCNT. 00: No change when compare-match B occurs 01: 0 is output when compare-match B occurs 10: 1 is output when compare-match B occurs 11: Output is inverted when compare-match B occurs (toggle output)
1 0
OS1 OS0
0 0
R/W R/W
Output Select 1 and 0 These bits specify how the timer output level is to be changed by a compare-match A of TCORA and TCNT. 00: No change when compare-match A occurs 01: 0 is output when compare-match A occurs 10: 1 is output when compare-match A occurs 11: Output is inverted when compare-match A occurs (toggle output)
Note:
*
Only a 0 can be written to this bit, to clear the flag.
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Section 11 8-Bit Timers
11.4
11.4.1
Operation
Pulse Output
Figure 11.2 shows an example of arbitrary duty cycle pulse output. 1. 2. Set TCR in CCR1 to 0 and CCLR0 to 1 to clear TCNT by a TCORA compare-match. Set OS3 to OS0 bits in TCSR to B'0110 to output 1 by a compare-match A and 0 by comparematch B.
By the above settings, waveforms with the cycle of TCORA and the pulse width of TCRB can be output without software intervention.
TCNT H'FF TCORA TCORB H'00 TMO Counter clear
Figure 11.2 Example of Pulse Output
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Section 11 8-Bit Timers
11.5
11.5.1
Operation Timing
TCNT Incrementation Timing
Figure 11.3 shows the TCNT count timing with internal clock source. Figure 11.4 shows the TCNT incrementation timing with external clock source. The pulse width of the external clock for incrementation at signal edge must be at least 1.5 system clock () periods, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values.
Internal clock
TCNT input clock
TCNT
N-1
N
N+1
Figure 11.3 Count Timing for Internal Clock Input
External clock input pin
TCNT input clock
TCNT
N-1
N
N+1
Figure 11.4 Count Timing for External Clock Input
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Section 11 8-Bit Timers
11.5.2
Timing of CMFA and CMFB Setting When a Compare-Match Occurs
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCOR and TCNT values match. The compare-match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare-match signal is not generated until the next incrementation clock input. Figure 11.5 shows the timing of CMF flag setting.
TCNT
N
N+1
TCOR Compare-match signal
N
CMF
Figure 11.5 Timing of CMF Setting 11.5.3 Timing of Timer Output When a Compare-Match Occurs
When a compare-match occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in TCSR. Figure 11.6 shows the timing when the output is set to toggle at comparematch A.
Compare-match A signal
Timer output pin
Figure 11.6 Timing of Timer Output
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Section 11 8-Bit Timers
11.5.4
Timing of Compare-Match Clear When a Compare-Match Occurs
TCNT is cleared when compare-match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 11.7 shows the timing of this operation.
Compare-match signal
TCNT
N
H'00
Figure 11.7 Timing of Compare-Match Clear 11.5.5 TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 11.8 shows the timing of this operation.
External reset input pin
Clear signal
TCNT
N-1
N
H'00
Figure 11.8 Timing of Clearing by External Reset Input
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Section 11 8-Bit Timers
11.5.6
Timing of Overflow Flag (OVF) Setting
OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 11.9 shows the timing of this operation.
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 11.9 Timing of OVF Setting
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Section 11 8-Bit Timers
11.6
Operation with Cascaded Connection
If bits CKS2 to CKS0 in one of TCR_1 and TCR_0, or TCR_3 and TCR_2 are set to B'100, the 8bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit timer mode) or compare-matches of 8-bit channel 0 (Channel 2) can be counted by the timer of channel 1 (Channel 3) (compare-match count mode). In the case that channel 0 is connected to channel 1 in cascade, the timer operates as described below. 11.6.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. * Setting of compare-match flags The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs. The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_1 and TCNT_0 together) is cleared when a 16-bit comparematch occurs. The 16-bit counter (TCNT_1 and TCNT_0 together) is cleared even if counter clear by the TMRI01 pin has also been set. The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. * Pin output Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare-match conditions. Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare-match conditions. 11.6.2 Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare-match A for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each channel.
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Section 11 8-Bit Timers
11.7
11.7.1
Interrupt Sources
Interrupt Sources and DTC Activation
The 8-bit timer can generate three types of interrupt: CMIA, CMIB, and OVI. Table 11.2 shows the interrupt sources and priority. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR. Independent signals are sent to the interrupt controller for each interrupt. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 11.2 8-Bit Timer Interrupt Sources
Interrupt source CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 CMIA2 CMIB2 OVI2 CMIA3 CMIB3 OVI3 Description TCORA_0 compare-match TCORB_0 compare-match TCNT_0 overflow TCORA_1 compare-match TCORB_1 compare-match TCNT_1 overflow TCORA_2 compare-match TCORB_2 compare-match TCNT_2 overflow TCORA_3 compare-match TCORB_3 compare-match TCNT_3 overflow Flag CMFA CMFB OVF CMFA CMFB OVF CMFA CMFB OVF CMFA CMFB OVF DTC Activation Possible Possible Not possible Possible Possible Not possible Possible Possible Not possible Possible Possible Not possible Low Interrupt Priority High
11.7.2
A/D Converter Activation
The A/D converter can be activated only by channel 0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of channel 0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started.
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Section 11 8-Bit Timers
11.8
11.8.1
Usage Notes
Conflict between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 11.10 shows this operation.
TCNT write cycle by CPU T1
T2
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 11.10 Conflict between TCNT Write and Clear
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Section 11 8-Bit Timers
11.8.2
Conflict between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 11.11 shows this operation.
TCNT write cycle by CPU T1 T2
Address TCNT address
Internal write signal
TCNT input clock
TCNT
N
M Counter write data
Figure 11.11 Conflict between TCNT Write and Increment
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Section 11 8-Bit Timers
11.8.3
Conflict between TCOR Write and Compare-Match
During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match occurs and the compare-match signal is disabled. Figure 11.12 shows this operation.
TCOR write cycle by CPU T1 T2
Address TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M TCOR write data
Compare-match signal Prohibited
Figure 11.12 Conflict between TCOR Write and Compare-Match 11.8.4 Conflict between Compare-Matches A and B
If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 11.3. Table 11.3 Timer Output Priorities
Output Setting Toggle output 1 output 0 output No change Low Priority High
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Section 11 8-Bit Timers
11.8.5
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 11.4 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 11.4, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. Erroneous incrementation can also happen when switching between internal and external clocks. Table 11.4 Switching of Internal Clock and TCNT Operation
Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from low to low*1
No. 1
TCNT Clock Operation
Clock before switchover Clock after switchover TCNT clock
TCNT
N CKS bit rewrite
N+1
2
Switching from low 2 to high*
Clock before switchover Clock after switchover TCNT clock
TCNT
N
N+1
N+2
CKS bit rewrite
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Section 11 8-Bit Timers Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to low*3
No. 3
TCNT Clock Operation
Clock before switchover Clock after switchover TCNT clock
*4
TCNT
N
N+1 CKS bit rewrite
N+2
4
Switching from high to high
Clock before switchover Clock after switchover TCNT clock
TCNT
N
N+1
N+2 CKS bit rewrite
Notes: 1. 2. 3. 4.
Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
11.8.6
Conflict between Interrupts and Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. 11.8.7 Notes on Cascaded Connection
If 16-bit count mode and compare-match count mode are set simultaneously, the counter stops and does not operate since input clocks of TCNT_1 and TCNT_0 (TCNT_3 and TCNT_2) are not generated. This setting is prohibited.
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Section 11 8-Bit Timers
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Section 12 Programmable Pulse Generator (PPG)
Section 12 Programmable Pulse Generator (PPG)
The programmable pulse generator provides pulse outputs using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 and group 2) that can operate both simultaneously and independently. The block diagram of the PPG is shown in figure 12.1.
12.1
* * * * * * *
Features
8-bit output data Two output groups Selectable output trigger signals Non-overlap mode Can operate in tandem with the data transfer controller (DTC) Settable inverted output Module stop mode can be set
PPG0000A_000020020300
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Section 12 Programmable Pulse Generator (PPG)
Compare match signals
NDERH Control logic PMR
NDERL PCR
PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8
Pulse output pins, group 3 PODRH Pulse output pins, group 2 Pulse output pins, group 1 PODRL Pulse output pins, group 0 NDRL NDRH
Internal data bus
Legend: PMR: PCR: NDERH: NDERL: NDRH: NDRL: PODRH: PODRL:
PPG output mode register PPG output control register Next data enable register H Next data enable register L Next data register H Next data register L Output data register H Output data register L
Figure 12.1 Block Diagram of PPG
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Section 12 Programmable Pulse Generator (PPG)
12.2
Input/Output Pins
Table 12.1 summarizes the pin configuration of the PPG. Table 12.1 Pin Configuration
Pin Name PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 I/O Output Output Output Output Output Output Output Output Group 2 pulse output Function Group 3 pulse output
12.3
Register Descriptions
The PPG has the following registers. * * * * * * * * PPG output control register (PCR) PPG output mode register (PMR) Next data enable register H (NDERH) Next data enable register L (NDERL) Output data register H (PODRH) Output data register L (PODRL) Next data register H (NDRH) Next data register L (NDRL)
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Section 12 Programmable Pulse Generator (PPG)
12.3.1
Next Data Enable Registers H, L (NDERH, NDERL)
NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis. The corresponding DDR also needs to be set to 1 in order to enable pulse output by the PPG. * NDERH
Bit 7 6 5 4 3 2 1 0 Bit Name NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 15 to 8 When a bit is set to 1 for pulse output by NDRH, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger. Values are not transferred from NDRH to PODRH for cleared bits.
* NDERL
Bit 7 6 5 4 3 2 1 0 Bit Name NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 7 to 0 When a bit is set to 1 for pulse output by NDRL, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits.
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Section 12 Programmable Pulse Generator (PPG)
12.3.2
Output Data Registers H, L (PODRH, PODRL)
PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. * PODRH
Bit 7 6 5 4 3 2 1 0 Bit Name POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 15 to 8 For bits that have been set to pulse output by NDERH, the output trigger transfers NDRH values to this register during PPG operation. While NDERH is set to 1, the CPU cannot write to this register. While NDERH is cleared, the initial output value of the pulse can be set.
* PODRL
Bit 7 6 5 4 3 2 1 0 Bit Name POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 7 to 0 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set.
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Section 12 Programmable Pulse Generator (PPG)
12.3.3
Next Data Registers H, L (NDRH, NDRL)
NDRH and NDRL are 8-bit readable/writable registers that store the data for the next pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. * NDRH If pulse output groups 3 and 2 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
Bit 7 6 5 4 3 2 1 0 Bit Name NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 15 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR.
If pulse output groups 3 and output pulse groups 2 have different output triggers, the upper 4 bits and the lower 4 bits are mapped to different addresses, as shown below.
Bit 7 6 5 4 3 to 0 Bit Name NDR15 NDR14 NDR13 NDR12 Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W Description Next Data Register 15 to 12 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. Reserved These bits are always read as 1 and cannot be modified.
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Section 12 Programmable Pulse Generator (PPG) Bit 7 to 4 3 2 1 0 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. NDR11 NDR10 NDR9 NDR8 0 0 0 0 R/W R/W R/W R/W Next Data Register 11 to 8 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR.
* NDRL If pulse output groups 1 and 0 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
Bit 7 6 5 4 3 2 1 0 Bit Name NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 7 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR.
If pulse output groups 1 and output pulse groups 0 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses as shown below.
Bit 7 6 5 4 Bit Name NDR7 NDR6 NDR5 NDR4 Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W Description Next Data Register 7 to 4 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Reserved These bits are always read as 1 and cannot be modified.
3 to 0
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Section 12 Programmable Pulse Generator (PPG) Bit 7 to 4 3 2 1 0 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. NDR3 NDR2 NDR1 NDR0 0 0 0 0 R/W R/W R/W R/W Next Data Register 3 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR.
12.3.4
PPG Output Control Register (PCR)
PCR is an 8-bit readable/writable register that selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 12.3.5, PPG Output Mode Register (PMR).
Bit 7 6 Bit Name G3CMS1 G3CMS0 Initial Value 1 1 R/W R/W R/W Description Group 3 Compare Match Select 1 and 0 Select output trigger of pulse output group 3. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 5 4 G2CMS1 G2CMS0 1 1 R/W R/W Group 2 Compare Match Select 1 and 0 Select output trigger of pulse output group 2. 00: Compare match in TPC channel 0 01: Compare match in TPC channel 1 10: Compare match in TPC channel 2 11: Compare match in TPC channel 3 3 2 1 0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 1 1 1 1 R/W R/W R/W R/W Reserved Reserved
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Section 12 Programmable Pulse Generator (PPG)
12.3.5
PPG Output Mode Register (PMR)
The PMR is an 8-bit readable/writable register that selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values on compare match A or B of the TPU that becomes the output trigger. For details, refer to section 12.4.5, Non-Overlapping Pulse Output.
Bit 7 Bit Name G3INV Initial Value 1 R/W R/W Description Group 3 Inversion Selects direct output or inverted output for pulse output group 3. 0: Inverted output 1: Direct output 6 G2INV 1 R/W Group 2 Inversion Selects direct output or inverted output for pulse output group 2. 0: Inverted output 1: Direct output 5, 4 3 G3NOV All 1 0 R/W R/W Reserved Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values at compare match A or B in the selected TPU channel) 2 G2NOV 0 R/W Group 2 Non-Overlap Selects normal or non-overlapping operation for pulse output group 2. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values at compare match A or B in the selected TPU channel) 1, 0 All 0 R/W Reserved
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Section 12 Programmable Pulse Generator (PPG)
12.4
12.4.1
Operation
Overview
Figure 12.2 shows a block diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. The sequential output of up to 8 bits of data is possible by writing new output data to NDR before the next compare match.
DDR
NDER Q Output trigger signal
C Q PODR D Pulse output pin Normal output/inverted output
Q NDR D
Internal data bus
Figure 12.2 PPG Output Operation
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Section 12 Programmable Pulse Generator (PPG)
12.4.2
Output Timing
If pulse output is enabled, the contents of NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 3 and 2, triggered by compare match A.
TCNT
N
N+1
TGRA
N
Compare match A signal
NDRH
n
PODRH
m
n
PO15 to PO8
m
n
Figure 12.3 Timing of Transfer and Output of NDR Contents (Example)
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Section 12 Programmable Pulse Generator (PPG)
12.4.3
Sample Setup Procedure for Normal Pulse Output
Figure 12.4 shows a sample procedure for setting up normal pulse output.
Normal PPG output Select TGR functions Set TGRA value TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Port and PPG setup Select output trigger Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [10] [3] [4] [5] [6] [7] [1] [2]
[1] Set TIOR to make TGRA an output compare register (with output disabled). [2] Set the PPG output trigger period. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR.
[8]
[9] No
Figure 12.4 Setup Procedure for Normal Pulse Output (Example)
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Section 12 Programmable Pulse Generator (PPG)
12.4.4
Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output.
TCNT value TGRA Compare match
TCNT
H'0000 NDRH 80 C0 40 60 20 30 10 18 08 88 80 C0 40
Time
PODRH
00
80
C0
40
60
20
30
10
18
08
88
80
C0
PO15
PO14
PO13
PO12
PO11
Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) 1. Set up TGRA of the TPU that is used as the output trigger to be an output compare register. Set a frequency in TGRA so the counter will be cleared on compare match A. Set the TGIEA bit of TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU.
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Section 12 Programmable Pulse Generator (PPG)
12.4.5
Non-Overlapping Pulse Output
During non-overlapping operation, transfer from NDR to PODR is performed as follows: * NDR bits are always transferred on PODR bits on compare match A. * On compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 12.6 illustrates the non-overlapping pulse output operation.
DDR
NDER Q Compare match A Compare match B
Pulse output pin
C Q PODR D
Q NDR D
Internal data bus
Normal output/inverted output
Figure 12.6 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval between compare match B and compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC. Note, however, that the next data must be written before the next compare match B occurs. Figure 12.7 shows the timing of this operation.
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Section 12 Programmable Pulse Generator (PPG)
Compare match A
Compare match B Write to NDR NDR Write to NDR
PODR 0 output 0/1 output 0 output 0/1 output Write to NDR here
Write to NDR Do not write here to NDR here
Do not write to NDR here
Figure 12.7 Non-Overlapping Operation and NDR Write Timing
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Section 12 Programmable Pulse Generator (PPG)
12.4.6
Sample Setup Procedure for Non-Overlapping Pulse Output
Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output.
Non-overlapping PPG output Select TGR functions Set TGR values TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set non-overlapping groups Set next pulse output data TPU setup Start counter Compare match A? Yes Set next pulse output data [11] [11] At each TGIA interrupt, set the next output values in NDR. [3] [4] [5] [6] [7] [8] [1] [2] [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled). [2] Set the pulse output trigger period in TGRB and the non-overlap margin in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlap mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter.
PPG setup
[9]
[10] No
Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example)
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Section 12 Programmable Pulse Generator (PPG)
12.4.7
Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output)
Figure 12.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output.
TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time
PODRH
00
95
05
65
41
59
50
56
14
95
05
65
Non-overlap margin PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
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Section 12 Programmable Pulse Generator (PPG)
1. Set up the TPU channel to be used as the output trigger channel such that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared on compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. 4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95, ... at successive TGIA interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU.
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Section 12 Programmable Pulse Generator (PPG)
12.4.8
Inverted Pulse Output
If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12.9.
TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time
PODRL
00
95
05
65
41
59
50
56
14
95
05
65
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 12.10 Inverted Pulse Output (Example)
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Section 12 Programmable Pulse Generator (PPG)
12.4.9
Pulse Output Triggered by Input Capture
Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 12.11 shows the timing of this output.
TIOC pin Input capture signal
NDR
N
PODR
M
N
PO
M
N
Figure 12.11 Pulse Output Triggered by Input Capture (Example)
12.5
12.5.1
Usage Notes
Module Stop Mode Setting
PPG operation can be disabled or enabled using the module stop control register. The initial setting is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes. 12.5.2 Operation of Pulse Output Pins
Pins PO15 to PO8 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur.
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Section 13 Watchdog Timer
Section 13 Watchdog Timer
The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI, if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagram of the WDT is shown in figure 13.1.
13.1
Features
* Selectable from eight counter input clocks. * Switchable between watchdog timer mode and interval timer mode In watchdog timer mode * If the counter overflows, it is possible to select whether this LSI is internally reset or not. In interval timer mode * If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
WDT0100A_000020020300
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Section 13 Watchdog Timer
Overflow WOVI (interrupt request signal) Interrupt control Clock Clock select
Internal reset signal*
Reset control
/2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock sources
Internal bus
RSTCSR
TCNT
TSCR Bus interface
Module bus WDT Legend: TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Note: * The type of internal reset signal depends on a register setting.
Figure 13.1 Block Diagram of WDT
13.2
Register Descriptions
The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to by a different method to normal registers. For details, refer to section 13.5.1, Notes on Register Access. * Timer control/status register (TCSR) * Timer counter (TCNT) * Reset control/status register (RSTCSR) 13.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the TME bit in TCSR is cleared to 0.
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Section 13 Watchdog Timer
13.2.2
Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be input to TCNT, and selecting the timer mode.
Bit 7 Bit Name OVF Initial Value 0 R/W R/(W)* Description Overflow Flag Indicates that TCNT has overflowed. Only a write of 0 is permitted, to clear the flag. [Setting condition] * When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing condition] * 6 WT/IT 0 R/W Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
Timer Mode Select Selects whether the WDT is used as a watchdog timer or an interval timer. 0: Interval timer mode 1: Watchdog timer mode
5
TME
0
R/W
Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00.
4, 3
All 1
Reserved These bits are always read as 1 and cannot be modified.
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Section 13 Watchdog Timer Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow frequency for = 20 MHz is enclosed in parentheses. 000: Clock /2 (frequency: 25.6 s) 001: Clock /64 (frequency: 819.2 s) 010: Clock /128 (frequency: 1.6 ms) 011: Clock /512 (frequency: 6.6 ms) 100: Clock /2048 (frequency: 26.2 ms) 101: Clock /8192 (frequency: 104.9 ms) 110: Clock /32768 (frequency: 419.4 ms) 111: Clock /131072 (frequency: 1.68 s) Note: * Only 0 can be written, for flag clearing.
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Section 13 Watchdog Timer
13.2.3
Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the pin, and not by the WDT internal reset signal caused by overflows.
Bit 7 Bit Name WOVF Initial Value 0
6
RSTE
0
5
RSTS
0
4 to 0 Note:
All 1
*
Only 0 can be written, for flag clearing.
SER
R/W R/(W)*
Description Watchdog Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] * Set when TCNT overflows (changed from H'FF to H'00) in watchdog timer mode Cleared by reading RSTCSR when WOVF = 1, and then writing 0 to WOVF
[Clearing condition] * R/W
Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation. 0: Reset signal is not generated even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: Reset signal is generated if TCNT overflows
R/W
Reset Select Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. 0: Power-on reset 1: Setting prohibited
Reserved These bits are always read as 1 and cannot be modified.
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Section 13 Watchdog Timer
13.3
13.3.1
Operation
Watchdog Timer Mode Operation
To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before overflow occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system malfunction or other error, the WOVF bit in RSTCSR is set to 1. If the RSTE bit in RSTCSR is set to 1, an internal reset is issued. This is shown in figure 13.2. At this time, select the power-on reset by clearing the RSTS bit in RSTCSR to 0. The internal reset signal is output for 518 states. pin occurs at the same time as a reset caused by a If a reset caused by a signal input to the WDT overflow, the reset by the pin has priority and the WOVF bit in RSTCSR is cleared to 0.
TCNT value Overflow H'FF
H'00 WT/IT=1 TME=1 Write H'00 to TCNT WOVF=1 internal reset is generated
Internal reset signal* 518 states Legend: WT/IT: Timer mode select bit TME: Timer enable bit Note: * The internal reset signal is generated only if the RSTE bit is set to 1.
Figure 13.2 Example of WDT0 Watchdog Timer Operation 13.3.2 Interval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals.
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SER
SER
Time WT/IT=1 TME=1 Write H'00 to TCNT
Section 13 Watchdog Timer
When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the time the OVF bit of the TCSR is set to 1.
13.4
Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Table 13.1 WDT Interrupt Source
Name WOVI Interrupt Source TCNT overflow Interrupt Flag WOVF DTC Activation Impossible
13.5
13.5.1
Usage Notes
Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT, TCSR, and RSTCSR: To write to TCNT and TCSR, execute a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, the relative condition shown in figure 13.3 needs to be satisfied in order to write to TCNT or TCSR. The transfer instruction writes the lower byte data to TCNT or TCSR according to the satisfied condition. To write to RSTCSR, execute a word transfer instruction for address H'FF76. A byte transfer instruction cannot write to RSTCSR. The method of writing 0 to the WOVF bit differs from that of writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, satisfy the condition shown in figure 13.3. If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to the RSTE and RSTS bits, satisfy the condition shown in figure 13.3. If satisfied, the transfer instruction writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits, respectively, but has no effect on the WOVF bit.
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Section 13 Watchdog Timer
TCNT write Writing to RSTE and RSTS bits Address: H'FF74 H'FF76 15 H'A5 8 7 Write data 0
TCSR write Writing 0 to WOVF bit Address: H'FF74 H'FF76 15 H'A5 8 7 0 Write data or H'00
Figure 13.3 Writing to TCNT, TCSR, and RSTCSR (Example for WDT0) Reading TCNT, TCSR, and RSTCSR (WDT0): These registers are read in the same way as other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR. 13.5.2 Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 13.4 shows this operation.
TCNT write cycle T1 T2
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 13.4 Conflict between TCNT Write and Increment
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Section 13 Watchdog Timer
13.5.3
Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 13.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 13.5.5 Internal Reset in Watchdog Timer Mode
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, however TCNT and TCSR of the WDT are reset. TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states after overflow to write 0 to the WOVF flag for clearing. 13.5.6 OVF Flag Clearing in Interval Timer Mode
When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0 to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before writing 0 to the OVF bit to clear the flag.
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Section 13 Watchdog Timer
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Section 14 Serial Communication Interface (SCI)
Section 14 Serial Communication Interface (SCI)
This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Figure 14.1 shows a block diagram of the SCI.
14.1
Features
* Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source (except for in Smart Card interface mode). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Transmit-end, transmit-data-empty, receive-data-full, and receive error that can issue requests. The transmit-data-empty interrupt and receive-data-full interrupt can be used to activate the data transfer controller (DTC). * Module stop mode can be set Asynchronous mode * Data length: 8 or 7 bits * Stop bit length: 2 or 1 bits * Parity: Even, odd, or none * Receive error detection: Parity, overrun, and framing errors
SCI0027A_0100020020900
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Section 14 Serial Communication Interface (SCI)
* Break detection: Break can be detected by reading the RxD pin level directly in the case of a framing error Clocked synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected Smart Card interface * Automatic transmission of error signal (parity error) in receive mode * Error signal detection and automatic data retransmission in transmit mode * Direct convention and inverse convention both supported
Bus interface
Module data bus
Internal data bus
RDR
TDR
SCMR SSR SCR
BRR Baud rate generator /4 /16 /64 Clock
RxD
RSR
TSR
SMR
Transmission/ reception control
TxD
Parity generation Parity check
SCK
External clock TEI TXI RXI ERI
Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register SCMR: Smart Card mode register BRR: Bit rate register
Figure 14.1 Block Diagram of SCI
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Section 14 Serial Communication Interface (SCI)
14.2
Input/Output Pins
Table 14.1 shows the serial pins for each SCI channel. Table 14.1 Pin Configuration
Channel 0 Pin Name* SCK0 RxD0 TxD0 2 SCK2 RxD2 TxD2 Note: * I/O I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation.
14.3
Register Descriptions
The SCI has the following registers for each channel. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions differ in part. * * * * * * * * * Receive Shift Register (RSR) Receive Data Register (RDR) Transmit Data Register (TDR) Transmit Shift Register (TSR) Serial Mode Register (SMR) Serial Control Register (SCR) Serial Status Register (SSR) Smart Card Mode Register (SCMR) Bit Rate Register (BRR)
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Section 14 Serial Communication Interface (SCI)
14.3.1
Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 14.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. 14.3.3 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. 14.3.4 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU.
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Section 14 Serial Communication Interface (SCI)
14.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bit functions of SMR differ between normal serial communication interface mode and Smart Card interface mode. * Normal Serial Communication Interface Mode (When SMIF in SCMR Is 0)
Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity
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Section 14 Serial Communication Interface (SCI) Bit 3 Bit Name STOP Initial Value 0 R/W R/W Description Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see 14.3.9, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see 14.3.9, Bit Rate Register (BRR)).
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Section 14 Serial Communication Interface (SCI)
* Smart Card Interface Mode (When SMIF in SCMR Is 1)
Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of one bit), and clock output control mode addition is performed. For details, refer to section 14.7.8, Clock Output Control. 6 BLK 0 R/W When this bit is set to 1, the SCI operates in block transfer mode. For details on block transfer mode, refer to section 14.7.3, Block Transfer Mode. Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data in transmission, and the parity bit is checked in reception. In Smart Card interface mode, this bit must be set to 1. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on setting this bit in Smart Card interface mode, refer to section 14.7.2, Data Format (Except for Block Transfer Mode). 3 2 BCP1 BCP0 0 0 R/W R/W Basic Clock Pulse 2 and 1 These bits specify the number of basic clock periods in a 1-bit transfer interval on the Smart Card interface. 00: 32 clock (S = 32) 01: 64 clock (S = 64) 10: 372 clock (S = 372) 11: 256 clock (S = 256) For details, refer to section 14.7.4, Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode. S stands for the value of S in BRR (see section 14.3.9, Bit Rate Register (BRR)).
5
PE
0
R/W
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Section 14 Serial Communication Interface (SCI) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W R/W Description Clock Select 1 and 0 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 14.3.9, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 14.3.9, Bit Rate Register (BRR)).
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Section 14 Serial Communication Interface (SCI)
14.3.6
Serial Control Register (SCR)
SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also used to selection of the transfer clock source. For details on interrupt requests, refer to section 14.8, Interrupt Sources. Some bit functions of SCR differ between normal serial communication interface mode and Smart Card interface mode. * Normal Serial Communication Interface Mode (When SMIF in SCMR Is 0)
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit s set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to 14.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable This bit is set to 1, TEI interrupt request is enabled.
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Section 14 Serial Communication Interface (SCI) Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 0 and 1 Selects the clock source and SCK pin function. Asynchronous mode 00: Internal baud rate generator SCK pin functions as I/O port 01: Internal baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK pin. 1x: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK pin. Clocked synchronous mode 0x: Internal clock (SCK pin functions as clock output) 1x: External clock (SCK pin functions as clock input) Legend: x: Don't care
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Section 14 Serial Communication Interface (SCI)
* Smart Card Interface Mode (When SMIF in SCMR Is 1)
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in Smart Card interface mode. 2 1 0 TEIE CKE1 CKE0 0 0 0 R/W R/W R/W Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode. Clock Enable 1 and 0 Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, refer to section 14.7.8, Clock Output Control. When the GM bit in SMR is 0 00: Output disabled (SCK pin can be used as an I/O port pin) 01: Clock output 1x: Reserved When the GM bit in SMR is 1 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output Legend: x: Don't care
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Section 14 Serial Communication Interface (SCI)
14.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ between normal serial communication interface mode and Smart Card interface mode. * Normal Serial Communication Interface Mode (When SMIF in SCMR Is 0)
Bit 7 Bit Name TDRE Initial Value 1 R/W R/W Description Transmit Data Register Empty Displays whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR
[Clearing conditions] * * When 0 is written to TDRE after reading TDRE =1 When the DTC is activated by a TXI interrupt request and writes data to TDR
6
RDRF
0
R/W
Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR
[Clearing conditions] * * When 0 is written to RDRF after reading RDRF = 1 When the DTC is activated by an RXI interrupt and transferred data from RDR
The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0.
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Section 14 Serial Communication Interface (SCI) Bit 5 Bit Name ORER Initial Value 0 R/W R/W Description Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1
[Clearing condition] * When 0 is written to ORER after reading ORER = 1
4
FER
0
R/W
Framing Error [Setting condition] * When the stop bit is 0
[Clearing condition] * When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked. 3 PER 0 R/W Parity Error [Setting condition] * When a parity error is detected during reception
[Clearing condition] * When 0 is written to PER after reading PER = 1
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Section 14 Serial Communication Interface (SCI) Bit 2 Bit Name TEND Initial Value 1 R/W R Description Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
[Clearing conditions] * * When 0 is written to TDRE after reading TDRE =1 When the DTC is activated by a TXI interrupt and writes data to TDR
1
MPB
0
R
Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit data.
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Section 14 Serial Communication Interface (SCI)
* Smart Card Interface Mode (When SMIF in SCMR Is 1)
Bit 7 Bit Name TDRE Initial Value 1 R/W R/W Description Transmit Data Register Empty Displays whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR
[Clearing conditions] * * When 0 is written to TDRE after reading TDRE =1 When the DTC is activated by a TXI interrupt request and writes data to TDR
6
RDRF
0
R/W
Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR
[Clearing conditions] * * When 0 is written to RDRF after reading RDRF = 1 When the DTC is activated by an RXI interrupt and transferred data from RDR
The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0.
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Section 14 Serial Communication Interface (SCI) Bit 5 Bit Name ORER Initial Value 0 R/W R/W Description Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1
[Clearing condition] * When 0 is written to ORER after reading ORER = 1
4
ERS
0
R/W
Error Signal Status [Setting condition] * When the low level of the error signal is sampled
[Clearing condition] * When 0 is written to ERS after reading ERS = 1
3
PER
0
R/W
Parity Error [Setting condition] * When a parity error is detected during reception
[Clearing condition] * When 0 is written to PER after reading PER = 1
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Section 14 Serial Communication Interface (SCI) Bit 2 Bit Name TEND Initial Value 1 R/W R Description Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions] * * When the TE bit in SCR is 0 and the ERS bit is also 0 When the ERS bit is 0 and the TDRE bit is 1 after the specified interval following transmission of 1-byte data. The timing of bit setting differs according to the register setting as follows: When GM = 0 and BLK = 0, 2.5 etu after transmission starts When GM = 0 and BLK = 1, 1.5 etu after transmission starts When GM = 1 and BLK = 0, 1.0 etu after transmission starts When GM = 1 and BLK = 1, 1.0 etu after transmission starts [Clearing conditions] * * When 0 is written to TDRE after reading TDRE =1 When the DTC is activated by a TXI interrupt and writes data to TDR
1 0
MPB MPBT
0 0
R R/W
Multiprocessor Bit This bit is not used in Smart Card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in Smart Card interface mode.
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Section 14 Serial Communication Interface (SCI)
14.3.8
Smart Card Mode Register (SCMR)
SCMR is a register that selects Smart Card interface mode and its format.
Bit 7 to 4 3 Bit Name SDIR Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1. Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits. For 7-bit data, LSB-first is fixed. 2 SINV 0 R/W Smart Card Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR 1 0 SMIF 1 0 R/W Reserved This bit is always read as 1. Smart Card Interface Mode Select This bit is set to 1 to make the SCI operate in Smart Card interface mode. 0: Normal asynchronous mode or clocked synchronous mode 1: Smart card interface mode
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Section 14 Serial Communication Interface (SCI)
14.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 14.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and it can be read or written to by the CPU at all times. Table 14.2 The Relationships between The N Setting in BRR and Bit Rate B
Mode Asynchronous Mode Clocked Synchronous Mode Smart Card Interface Mode Legend: B: N: : n and S: BRR Setting N
N= x 106 64 x 2 2n-1 x B x 106 8 x 2 2n-1 x B
x 106 Sx2
2n+1
Error
-1
Error (%) = {
x 106 B x 64 x 2 2n-1 x (N + 1)
- 1 } x 100
N=
-1
N=
xB
-1
Error (%) = {
x 106 B x S x 2 2n+1 x (N + 1)
- 1 } x 100
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Determined by the SMR settings shown in the following tables. SMR Setting n 0 1 2 3 BCP1 0 0 1 1 BCP0 0 1 0 1 S 32 64 372 256
SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1
Table 14.3 shows sample N settings in BRR in normal asynchronous mode. Table 14.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 14.6 shows sample N settings in BRR in clocked synchronous mode. Table 14.8 shows sample N settings in BRR in Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in a 1-bit transfer interval) can be selected. For details, refer to section 14.7.4, Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode. Tables 14.5 and 14.7 show the maximum bit rates with external clock input.
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Section 14 Serial Communication Interface (SCI)
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 4 n 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 4.9152 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73
Operating Frequency (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 7.3728 N 130 95 191 95 191 95 47 23 11 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 2 2 1 1 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00
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Section 14 Serial Communication Interface (SCI)
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency (MHz) 9.8304 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00
Operating Frequency (MHz) 14 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 Error (%) -0.17 0.13 0.13 0.13 0.13 0.13 0.13 -0.93 -0.93 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.00 0.13 n 3 2 2 1 1 0 0 0 0 0 0 17.2032 N 75 223 111 223 111 223 111 55 27 13 13 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00
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Section 14 Serial Communication Interface (SCI)
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
Operating Frequency (MHz) 18 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 24 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 -2.34
Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
(MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 230400 250000 307200 312500 n 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 (MHz) 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 24 Maximum Bit Rate (bit/s) 375000 384000 437500 460800 500000 537600 562500 614400 625000 750000 n 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0
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Section 14 Serial Communication Interface (SCI)
Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
(MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 External Input Clock (MHz) 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 Maximum Bit Rate (bit/s) 62500 76800 78125 93750 96000 115200 125000 153600 156250 (MHz) 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 24 External Input Clock (MHz) 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 6.0000 Maximum Bit Rate (bit/s) 187500 192000 218750 230400 250000 268800 281250 307200 312500 375000
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Section 14 Serial Communication Interface (SCI)
Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M Legend: Blank: Setting prohibited. : Can be set, but there will be a degree of error. *: Continuous transfer is not possible. 4 n 2 2 1 1 0 0 0 0 0 0 0 0 N 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* 1 1 0 0 0 0 0 0 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 2 1 1 0 0 0 0 0 0 0 0 124 249 124 199 99 49 19 9 4 1 0* 2 2 1 1 1 0 0 0 0 149 74 149 59 29 59 23 11 5 n 8 N n 10 N n 16 N n 20 N n 24 N
Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
(MHz) 4 6 8 10 12 External Input Clock (MHz) 0.6667 1.0000 1.3333 1.6667 2.0000 Maximum Bit Rate (bit/s) 666666.7 1.000000.0 1333333.3 1666666.7 2000000.0 (MHz) 14 16 18 20 24 External Input Clock (MHz) 2.3333 2.6667 3.0000 3.3333 4 Maximum Bit Rate (bit/s) 2333333.3 2666666.7 3000000.0 3333333.3 4000000.0
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Section 14 Serial Communication Interface (SCI)
Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372)
Operating Frequency (MHz) 7.1424 Bit Rate (bit/s) 9600 n 0 N 0 Error (%) 0.00 n 0 10.00 N 1 Error (%) 30 n 0 10.7136 N 1 Error (%) 25 n 0 13.00 N 1 Error (%) 8.99
Operating Frequency (MHz) 14.2848 Bit Rate (bit/s) 9600 n 0 N 1 Error (%) 0.00 n 0 16.00 N 1 Error (%) 12.01 n 0 18.00 N 2 Error (%) 15.99 n 0 20.00 N 2 Error (%) 6.60 n 0 24.00 N 2 Error (%) 12.01
Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (When S = 372)
(MHz) 7.1424 10.00 10.7136 13.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 n 0 0 0 0 N 0 0 0 0 (MHz) 14.2848 16.00 18.00 20.00 24.00 Maximum Bit Rate (bit/s) 19200 21505 24194 26882 32258 n 0 0 0 0 0 N 0 0 0 0 0
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Section 14 Serial Communication Interface (SCI)
14.4
Operation in Asynchronous Mode
Figure 14.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transfer/receive data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line. When the transmission line goes to the space state (low level), the SCI recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
Idle state (mark state) 1 0/1 Parity bit 1 bit, or none 1 1
1 Serial data 0 Start bit 1 bit
LSB D0 D1 D2 D3 D4 D5 D6
MSB D7
Stop bit
Transmit/receive data 8 or 7 bits
2 or 1 bits
One unit of transfer data (character or frame)
Figure 14.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 14.4.1 Data Transfer Format
Table 14.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 14.5, Multiprocessor Communication Function.
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Section 14 Serial Communication Interface (SCI)
Table 14.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S S S S S S S S S S S S 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10
STOP
11
12
8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data
STOP
STOP STOP
P STOP
P STOP STOP
STOP STOP
P
STOP
P
STOP STOP
MPB STOP
MPB STOP STOP
MPB STOP
MPB STOP STOP
Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit
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Section 14 Serial Communication Interface (SCI)
14.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 14.3. Thus, the reception margin in asynchronous mode is given by formula (1) below.
M = { (0.5 - D - 0.5 1 )- N 2N - (L - 0.5) F} x 100 [%]
... Formula (1) Where N: D: L: F: Ratio of bit rate to clock (N = 16) Clock duty cycle (D = 0.5 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty cycle) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 30% to 20% should be allowed for in system design.
16 clocks 8 clocks 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0
Start bit
D0
D1
Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode
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Section 14 Serial Communication Interface (SCI)
14.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 14.4.
SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 frame
Figure 14.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode)
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Section 14 Serial Communication Interface (SCI)
14.4.4
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization.
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
[4]
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR (TE and RE bits are cleared to 0.)
[1]
Set data transfer format in SMR and SCMR Set value in BRR Wait
[2]
[3]
No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits

Figure 14.5 Sample SCI Initialization Flowchart
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Section 14 Serial Communication Interface (SCI)
14.4.5
Data Transmission (Asynchronous Mode)
Figure 14.6 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 14.7 shows a sample flowchart for transmission in asynchronous mode.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1
1
1 Idle state (mark state)
TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt service routine
TEI interrupt request generated
1 frame
Figure 14.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
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Section 14 Serial Communication Interface (SCI)
Initialization Start transmission
[1]
Read TDRE flag in SSR
[2]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0.
No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No All data transmitted? Yes [3] Read TEND flag in SSR
No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1
[4]
Clear TE bit in SCR to 0
Figure 14.7 Sample Serial Transmission Flowchart
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Section 14 Serial Communication Interface (SCI)
14.4.6
Serial Data Reception (Asynchronous Mode)
Figure 14.8 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0
1
1 Idle state (mark state)
RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ERI interrupt request generated by framing error
1 frame
Figure 14.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)
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Section 14 Serial Communication Interface (SCI)
Table 14.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.9 shows a sample flowchart for serial data reception. Table 14.11 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
The RDRF flag retains the state it had before data reception.
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Section 14 Serial Communication Interface (SCI)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
[2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PERFERORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No Error processing resumed if any of these flags are set to 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin.
Read ORER, PER, and FER flags in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
[4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when DTC is activated by an RXI interrupt and the RDR value is read.
No All data received? Yes Clear RE bit in SCR to 0 [5]
Figure 14.9 Sample Serial Reception Data Flowchart (1)
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Section 14 Serial Communication Interface (SCI)
[3] Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
No PER = 1 Yes Parity error processing
Clear ORER, PER, and FER flags in SSR to 0

Figure 14.9 Sample Serial Reception Data Flowchart (2)
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Section 14 Serial Communication Interface (SCI)
14.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 14.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.
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Section 14 Serial Communication Interface (SCI)
Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) Receiving station C (ID = 03) H'AA (MPB = 0) Receiving station D (ID = 04)
ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID Legend: MPB: Multiprocessor bit
Figure 14.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 14.5.1 Multiprocessor Serial Data Transmission
Figure 14.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
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Section 14 Serial Communication Interface (SCI)
Initialization Start transmission
[1]
Read TDRE flag in SSR
[2]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to 1, clear DR to 0, then clear the TE bit in SCR to 0.
No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR
Clear TDRE flag to 0
No All data transmitted? Yes [3]
Read TEND flag in SSR
No TEND = 1 Yes No Break output? Yes [4]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0

Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart 14.5.2 Multiprocessor Serial Data Reception
Figure 14.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data
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Section 14 Serial Communication Interface (SCI)
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 14.12 shows an example of SCI operation for multiprocessor format reception.
Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data1) D1 D7 Stop MPB bit 0
1
1
1 Idle state (mark state)
MPIE
RDRF
RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state
(a) Data does not match station's ID
1
Start bit 0 D0 D1
Data (ID2) D7
Stop MPB bit 1 1
Start bit 0 D0
Data (Data2) D1 D7
Stop MPB bit 0
1
1 Idle state (mark state)
MPIE
RDRF
RDR value
ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine
ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine
Data2 MPIE bit set to 1 again
(b) Data matches station's ID
Figure 14.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 14 Serial Communication Interface (SCI)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin [4] value.
Read MPIE bit in SCR Read ORER and FER flags in SSR
[2]
FER ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR
Yes
[3]
FER ORER = 1 No Read RDRF flag in SSR
Yes
No RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 (Continued on next page)
[5] Error processing
Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 14 Serial Communication Interface (SCI)
[5]
Error processing
No ORER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0
Clear ORER, PER, and FER flags in SSR to 0

Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 14 Serial Communication Interface (SCI)
14.6
Operation in Clocked Synchronous Mode
Figure 14.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. Each character of data transferred consists of 8 bits. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronous with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 14.14 Data Format in Synchronous Communication (For LSB-First) 14.6.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of CKE0 and CKE1 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high.
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Section 14 Serial Communication Interface (SCI)
14.6.2
SCI Initialization (Clocked Synchronous Mode)
Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, then the SCI should be initialized as described in a sample flowchart in figure 14.15. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Start initialization
[1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, MPIE, TE, and RE, to 0. [2] Set the data transfer format in SMR and SCMR.
[1]
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR (TE, RE bits 0)
[3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
Set data transfer format in SMR and SCMR Set value in BRR Wait
[2]
[3]
No 1-bit interval elapsed? Yes
Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits
[4]

Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously.
Figure 14.15 Sample SCI Initialization Flowchart
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Section 14 Serial Communication Interface (SCI)
14.6.3
Serial Data Transmission (Clocked Synchronous Mode)
Figure 14.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. Continuous transmission is possible because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has been completed. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 14.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags.
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Section 14 Serial Communication Interface (SCI)
Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 14.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
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Section 14 Serial Communication Interface (SCI)
Initialization Start transmission
[1]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR.
Read TDRE flag in SSR
[2]
No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
No All data transmitted? Yes [3]
Read TEND flag in SSR
No TEND = 1 Yes Clear TE bit in SCR to 0
Figure 14.17 Sample Serial Transmission Flowchart
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Section 14 Serial Communication Interface (SCI)
14.6.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 14.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in RSR. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. 3. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished.
Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 14.18 Example of SCI Operation in Reception Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.19 shows a sample flow chart for serial data reception.
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Section 14 Serial Communication Interface (SCI)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. The RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read.
Read ORER flag in SSR
[2]
Yes ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR [4]
No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
No All data received? Yes Clear RE bit in SCR to 0 [5]
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
Figure 14.19 Sample Serial Reception Flowchart
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Section 14 Serial Communication Interface (SCI)
14.6.5
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
Figure 14.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after initializing the SCI. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
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Section 14 Serial Communication Interface (SCI)
Initialization Start transmission/reception
[1]
[1]
SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read.
Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
[2]
[2]
[3]
Read ORER flag in SSR Yes [3] Error processing
ORER = 1 No
[4]
Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
[4]
[5]
No All data received? Yes [5]
Clear TE and RE bits in SCR to 0
Note: * When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Figure 14.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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Section 14 Serial Communication Interface (SCI)
14.7
Operation in Smart Card Interface
The SCI supports an IC card (Smart Card) interface that conforms to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface mode is carried out by means of a register setting. 14.7.1 Pin Connection Example
Figure 14.21 shows an example of connection with the Smart Card. In communication with an IC card, as both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected to the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal.
VCC TxD RxD SCK Rx (port) This LSI Connected equipment Data line Clock line Reset line I/O CLK RST IC card
Figure 14.21 Schematic Diagram of Smart Card Interface Pin Connections
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Section 14 Serial Communication Interface (SCI)
14.7.2
Data Format (Except for Block Transfer Mode)
Figure 14.22 shows the transfer data format in Smart Card interface mode. * One frame consists of 8-bit data plus a parity bit in asynchronous mode. * In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. * If an error signal is sampled during transmission, the same data is retransmitted automatically after a delay of 2 etu or longer.
When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transmitting station output
When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Transmitting station output Receiving station output Start bit Data bits Parity bit Error signal
Legend: DS: D0 to D7: Dp: DE:
Figure 14.22 Normal Smart Card Interface Data Format
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Section 14 Serial Communication Interface (SCI)
Data transfer with other types of IC cards (direct convention and inverse convention) are performed as described in the following.
(Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State
Figure 14.23 Direct Convention (SDIR = SINV = O/E = 0) With the direction convention type IC and the above sample start character, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode.
(Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State
Figure 14.24 Inverse Convention (SDIR = SINV = O/E = 1) With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data for the above is H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to Smart Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z. In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/E bit in SMR to 1 to invert the parity bit for both transmission and reception.
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Section 14 Serial Communication Interface (SCI)
14.7.3
Block Transfer Mode
Operation in block transfer mode is the same as that in SCI asynchronous mode, except for the following points. * In reception, though the parity check is performed, no error signal is output even if an error is detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the parity bit of the next frame. * In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame. * In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu after transmission start. * As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since error signal transfer is not performed, this flag is always cleared to 0. 14.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode
In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. As shown in figure 14.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the following formula.
M = | (0.5 - | D - 0.5 | 1 ) - (L - 0.5) F - (1 + F) | x 100% N 2N
Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, and 256) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. M = (0.5 - 1/2 x 372) x 100% = 49.866%
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Section 14 Serial Communication Interface (SCI)
372 clocks 186 clocks 0 Internal basic clock 185 371 0 185 371 0
Receive data (RxD) Synchronization sampling timing
Start bit
D0
D1
Data sampling timing
Figure 14.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) 14.7.5 Initialization
Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3. Set the GM, BLK, O/E, BCP0, BCP1, CKS0, CKS1 bits in SMR. Set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. To switch from receive mode to transmit mode, after checking that the SCI has finished reception, initialize the SCI, and set RE to 0 and TE to 1. Whether SCI has finished reception or not can be checked with the RDRF, PER, or ORER flags. To switch from transmit mode to receive mode,
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Section 14 Serial Communication Interface (SCI)
after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to 1. Whether SCI has finished transmission or not can be checked with the TEND flag. 14.7.6 Data Transmission (Except for Block Transfer Mode)
As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 14.26 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sent back from the receiving end after transmission of one frame is complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. 2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality is received. Data is retransferred from TDR to TSR, and retransmitted automatically. 3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. Transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. Writing transmit data to TDR transfers the next transmit data. Figure 14.28 shows a flowchart for transmission. The sequence of transmit operations can be performed automatically by specifying the DTC to be activated with a TXI interrupt source. In a transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data is transferred by the DTC. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC is not activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DTC, it is essential to set and enable the DTC before carrying out SCI setting. For details of the DTC setting procedures, refer to section 8, Data Transfer Controller (DTC).
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Section 14 Serial Communication Interface (SCI)
nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7]
Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE)
Transfer frame n+1 Ds D0 D1 D2 D3 D4
Transfer to TSR from TDR
Transfer to TSR from TDR [9]
FER/ERS
[6] [8]
Figure 14.26 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 14.27.
I/O data TXI (TEND interrupt) When GM = 0
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE Guard time
12.5 etu
11.0 etu When GM = 1
Legend: Ds: D0 to D7: Dp: DE:
Start bit Data bits Parity bit Error signal
Figure 14.27 TEND Flag Generation Timing in Transmission Operation
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Section 14 Serial Communication Interface (SCI)
Start
Initialization Start transmission
ERS = 0? Yes
No
Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0
No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0
End
Figure 14.28 Example of Transmission Processing Flow
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Section 14 Serial Communication Interface (SCI)
14.7.7
Serial Data Reception (Except for Block Transfer Mode)
Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 14.29 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. 2. The RDRF bit in SSR is not set for a frame in which an error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. Figure 14.30 shows a flowchart for reception. A sequence of receive operations can be performed automatically by specifying the DTC to be activated using an RXI interrupt source. In a receive operation, an RXI interrupt request is generated when the RDRF flag is set to 1 if the RIE bit is set to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be activated by the RXI request, and the receive data will be transferred. The RDRF flag is cleared to 0 automatically when data is transferred by the DTC. If an error occurs in receive mode and the ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. Hence, so the error flag must be cleared to 0. In the event of an error, the DTC is not activated and receive data is skipped. Therefore, receive data is transferred for only the specified number of bytes in the event of an error. Even when a parity error occurs in receive mode and the PER flag is set to 1, the data that has been received is transferred to RDR and can be read from there. Note: For details on receive operations in block transfer mode, refer to 14.4, Operation in Asynchronous Mode.
Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4
nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1]
Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
[4]
[3]
Figure 14.29 Retransfer Operation in SCI Receive Mode
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Section 14 Serial Communication Interface (SCI)
Start
Initialization
Start reception
ORER = 0 and PER = 0 Yes
No
Error processing No
RDRF = 1? Yes
Read RDR and clear RDRF flag in SSR to 0
No
All data received? Yes Clear RE bit to 0
Figure 14.30 Example of Reception Processing Flow
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Section 14 Serial Communication Interface (SCI)
14.7.8
Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 14.31 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 14.31 Timing for Fixing Clock Output Level When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty cycle. Powering On: To secure clock duty cycle from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. 2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR. 3. Set SMR and SCMR, and switch to smart card mode operation. 4. Set the CKE0 bit in SCR to 1 to start clock output.
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Section 14 Serial Communication Interface (SCI)
When changing from smart card interface mode to software standby mode: 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. 2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to halt the clock. 4. Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty cycle preserved. 5. Make the transition to the software standby state. When returning to smart card interface mode from software standby mode: 1. Exit the software standby state. 2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty cycle.
Software standby
Normal operation
Normal operation
[1] [2] [3]
[4] [5]
[6] [7]
Figure 14.32 Clock Halt and Restart Procedure
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Section 14 Serial Communication Interface (SCI)
14.8
14.8.1
Interrupt Sources
Interrupts in Normal Serial Communication Interface Mode
Table 14.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data is transferred by the DTC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt request can activate the DTC to transfer data. The RDRF flag is cleared to 0 automatically when data is transferred by the DTC. A TEI interrupt is requested when the TEND flag is set to 1 and the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 14.12 SCI Interrupt Sources
Channel 0 Name ERI_0 RXI_0 TXI_0 TEI_0 2 ERI_2 RXI_2 TXI_2 TEI_2 Interrupt Source Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible
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Section 14 Serial Communication Interface (SCI)
14.8.2
Interrupts in Smart Card Interface Mode
Table 14.13 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 14.13 SCI Interrupt Sources
Channel 0 Name ERI_0 RXI_0 TXI_0 2 ERI_2 RXI_2 TXI_2 Interrupt Source Receive Error, error signal detection Receive Data Full Transmit Data Empty Receive Error, error signal detection Receive Data Full Transmit Data Empty Interrupt Flag ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND DTC Activation Not possible Possible Possible Not possible Possible Possible
In Smart Card interface mode, as in normal serial communication interface mode, transfer can be carried out using the DTC. In transmit operations, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR is set, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transmit data will be transferred. The TDRE and TEND flags are automatically cleared to 0 when data is transferred by the DTC. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC is not activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs. Hence, the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When transferring using the DTC, it is essential to set and enable the DTC before carrying out SCI setting. For details of the DTC setting procedures, refer to section 8, Data Transfer Controller (DTC). In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be activated by the RXI request, and the receive data will be transferred. The RDRF flag is cleared to 0 automatically when data is transferred by the DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC is not activated, instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared.
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Section 14 Serial Communication Interface (SCI)
14.9
14.9.1
Usage Notes
Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes. 14.9.2 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 14.9.3 Mark State and Break Detection
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 14.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
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Section 15 Controller Area Network (HCAN)
Section 15 Controller Area Network (HCAN)
The HCAN is a module for controlling a controller area network (CAN) for realtime communication in vehicular and industrial equipment systems, etc. For details on CAN specification, refer to Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH. The block diagram of the HCAN is shown in figure 15.1.
15.1
Features
* CAN version: Bosch 2.0B active compatible Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function) Broadcast communication system Transmission path: Bidirectional 2-wire serial communication Communication speed: Max. 1 Mbps Data length: 8 to 0 bytes * Number of channels: 1 * Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception) * Data transmission: Two methods Mailbox (buffer) number order (low-to-high) Message priority (identifier) reverse-order (high-to-low) * Data reception: Two methods Message identifier match (transmit/receive-setting buffers) Reception with message identifier masked (receive-only) * CPU interrupts: 12 Error interrupt Reset processing interrupt Message reception interrupt Message transmission interrupt * HCAN operating modes * Support for various modes Hardware reset Software reset Normal status (error-active, error-passive) Bus off status HCAN configuration mode
IFCAN00C_000020020900
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Section 15 Controller Area Network (HCAN)
HCAN sleep mode HCAN halt mode * Other features DTC can be activated by message reception mailbox (HCAN mailbox 0 only) * Module stop mode can be set
HCAN
Peripheral address bus
Peripheral data bus
MBI Message buffer Mailboxes Message control Message data MC15 to MC0, MD15 to MD0
LAFM
(CDLC) CAN Data Link Controller Bosch CAN 2.0B active HTxD
Tx buffer
MPI Microprocessor interface CPU interface Control register Status register
Rx buffer
HRxD
Figure 15.1 HCAN Block Diagram * Message Buffer Interface (MBI) The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.) Transmit messages are written by the CPU. For receive messages, the data received by the CDLC is stored automatically. * Microprocessor Interface (MPI) The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN internal data, status, and so forth. * CAN Data Link Controller (CDLC) The CDLC, conforming to the Bosch CAN Ver. 2.0B active standard, performs transmission and reception of messages (data frames, remote frames, error frames, overload frames, interframe spacing), as well as CRC checking, bus arbitration, and other functions.
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Section 15 Controller Area Network (HCAN)
15.2
Input/Output Pins
Table 15.1 shows the HCAN's pins. When using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 15.1 HCAN Pins
Name HCAN transmit data pin HCAN receive data pin Abbreviation HTxD HRxD Input/Output Output Input Function CAN bus transmission pin CAN bus reception pin
A bus driver is necessary for the interface between the pins and the CAN bus. A Philips PCA82C250 compatible model is recommended.
15.3
Register Descriptions
The HCAN has the following registers. * * * * * * * * * * * * * * * * * Master control register (MCR) General status register (GSR) Bit configuration register (BCR) Mailbox configuration register (MBCR) Transmit wait register (TXPR) Transmit wait cancel register (TXCR) Transmit acknowledge register (TXACK) Abort acknowledge register (ABACK) Receive complete register (RXPR) Remote request register (RFPR) Interrupt register (IRR) Mailbox interrupt mask register (MBIMR) Interrupt mask register (IMR) Receive error counter (REC) Transmit error counter (TEC) Unread message status register (UMSR) Local acceptance filter mask L (LAFML)
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Section 15 Controller Area Network (HCAN)
* * * *
Local acceptance filter mask H (LAFMH) Message control (8 bit x 8 registers x 16 sets) (MC15 to MC0) Message data (8 bit x 8 registers x 16 sets) (MD15 to MD0) HCAN Monitor Register (HCANMON) Master Control Register (MCR)
15.3.1
MCR is an 8-bit register that controls the HCAN.
Bit 7 Bit Name MCR7 Initial Value 0 R/W R/W Description HCAN Sleep Mode Release When this bit is set to 1, the HCAN automatically exits HCAN sleep mode on detection of CAN bus operation. 6 0 R Reserved This bit is always read as 0. The write value should always be 0. 5 MCR5 0 R/W HCAN Sleep Mode When this bit is set to 1, the HCAN transits to HCAN sleep mode. When this bit is cleared to 0, HCAN sleep mode is released. 4, 3 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 MCR2 0 R/W Message Transmission Method 0: Transmission order determined by message identifier priority 1: Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) 1 MCR1 0 R/W Halt Request When this bit is set to 1, the HCAN transits to HCAN HALT mode. When this bit is cleared to 0, HCAN HALT mode is released.
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Section 15 Controller Area Network (HCAN) Bit 0 Bit Name MCR0 Initial Value 1 R/W R/W Description Reset Request When this bit is set to 1, the HCAN transits to reset mode. For details, refer to 15.4.1, Hardware and Software Resets. [Setting condition] * 1-write (software reset)
[Clearing condition] * When 0 is written to this bit while the GSR3 bit in GSR is 1
15.3.2
General Status Register (GSR)
GSR is an 8-bit register that indicates the status of the CAN bus.
Bit 7 to 4 3 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. GSR3 1 R Reset Status Bit Indicates whether the HCAN module is in the normal operation state or the reset state. This bit cannot be modified. [Setting conditions] * * When entering configuration mode after the HCAN internal reset has finished Sleep mode
[Clearing condition] * When entering the normal operation state after the MCR0 bit in MCR is cleared to 0 (Note that there is a delay between clearing of the MCR0 bit and the GSR3 bit).
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Section 15 Controller Area Network (HCAN) Bit 2 Bit Name GSR2 Initial Value 1 R/W R Description Message Transmission Status Flag Flag that indicates whether the module is currently in the message transmission period. This bit cannot be modified. [Setting condition] * Third bit of Intermission after EOF (End of Frame)
[Clearing condition] * 1 GSR1 0 R Start of message transmission (SOF)
Transmit/Receive Warning Flag This bit cannot be modified. [Clearing condition] * When TEC < 96 and REC < 96 or TEC 256 (bus off state)
[Setting condition] * 0 GSR0 0 R When TEC 96 or REC 96
Bus Off Flag This bit cannot be modified. [Setting condition] * When TEC 256 (bus off state)
[Clearing condition] * Recovery from bus off state
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Section 15 Controller Area Network (HCAN)
15.3.3
Bit Configuration Register (BCR)
BCR is a 16-bit register that is used to set HCAN bit timing parameters and the baud rate prescaler. For details on parameters, refer to section 15.4.2, Initialization after Hardware Reset.
Bit 15 14 Bit Name BCR7 BCR6 Initial Value 0 0 R/W R/W R/W Description Re-Synchronization Jump Width (SJW) Set the maximum bit synchronization width. 00: 1 time quantum 01: 2 time quanta 10: 3 time quanta 11: 4 time quanta 13 12 11 10 9 8 7 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 BCR15 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Baud Rate Prescaler (BRP) Set the length of time quanta. 000000: 2 x system clock 000001: 4 x system clock 000010: 6 x system clock : 111111: 128 x system clock Bit Sample Point (BSP) Sets the point at which data is sampled. 0: Bit sampling at one point (end of time segment 1 (TSEG1)) 1: Bit sampling at three points (end of TSEG1 and preceding and following time quanta) 6 5 4 BCR14 BCR13 BCR12 0 0 0 R/W R/W R/W Time Segment 2 (TSEG2) Set the TSEG2 width within a range of 2 to 8 time quanta. 000: Setting prohibited 001: 2 time quanta 010: 3 time quanta 011: 4 time quanta 100: 5 time quanta 101: 6 time quanta 110: 7 time quanta 111: 8 time quanta
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Section 15 Controller Area Network (HCAN) Bit 3 2 1 0 Bit Name BCR11 BCR10 BCR9 BCR8 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Time Segment 1 (TSEG1) Set the TSEG1 (PRSEG + PHSEG1) width to between 16 and 4 time quanta. 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: 4 time quanta 0100: 5 time quanta 0101: 6 time quanta 0110: 7 time quanta 0111: 8 time quanta 1000: 9 time quanta 1001: 10 time quanta 1010: 11 time quanta 1011: 12 time quanta 1100: 13 time quanta 1101: 14 time quanta 1110: 15 time quanta 1111: 16 time quanta
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Section 15 Controller Area Network (HCAN)
15.3.4
Mailbox Configuration Register (MBCR)
MBCR is a 16-bit register that is used to set the transfer direction for each mailbox.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 Initial Value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Description These bits set the transfer direction for the corresponding mailboxes 15 to 1. MBCRn determines the transfer direction for mailbox n (n = 15 to 1). 0: Corresponding mailbox is set for transmission 1: Corresponding mailbox is set for reception Bit 8 is reserved. This bit is always read as 1. The write value should always be 1.
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Section 15 Controller Area Network (HCAN)
15.3.5
Transmit Wait Register (TXPR)
TXPR is a 16-bit register that is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait).
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Bit 8 is reserved. This bit is always read as 1. The write value should always be 1. Description These bits set a transmit wait (CAN bus arbitration wait) for the corresponding mailboxes 15 to 1. When TXPRn (n = 15 to 1) is set to 1, the message in mailbox n becomes the transmit wait state. [Clearing conditions] * * Completion of message transmission Completion of transmission cancellation
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Section 15 Controller Area Network (HCAN)
15.3.6
Transmit Wait Cancel Register (TXCR)
TXCR is a 16-bit register that controls the cancellation of transmit wait messages in mailboxes (buffers).
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Bit 8 is reserved. This bit is always read as 0. The write value should always be 0. Description These bits cancel the transmit wait message in the corresponding mailboxes 15 to 1. When TXCRn (n = 15 to 1) is set to 1, the transmit wait message in mailbox n is canceled. [Clearing condition] * Completion of TXPR clearing when transmit message is canceled normally
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Section 15 Controller Area Network (HCAN)
15.3.7
Transmit Acknowledge Register (TXACK)
TXACK is a 16-bit register containing status flags that indicate the normal transmission of mailbox (buffer) transmit messages.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: Bit Name TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 * Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description These bits are status flags that indicate error-free transmission of the transmit message in the corresponding mailboxes 15 to 1. When the message in mailbox n (n = 15 to 1) has been transmitted error-free, TXACKn is set to 1. [Setting condition] * Completion of message transmission for corresponding mailbox
[Clearing condition] * Writing 1
Bit 8 is reserved. This bit is always read as 0. The write value should always be 0.
Only 1 can be written to clear the flag.
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Section 15 Controller Area Network (HCAN)
15.3.8
Abort Acknowledge Register (ABACK)
ABACK is a 16-bit register containing status flags that indicate the normal cancellation (aborting) of mailbox (buffer) transmit messages.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: Bit Name ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 * Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description These bits are status flags that indicate error-free cancellation (abortion) of the transmit message in the corresponding mailboxes 15 to 1. When the message in mailbox n (n = 15 to 1) has been canceled error-free, ABACKn is set to 1. [Setting condition] * Completion of transmit message cancellation for corresponding mailbox
[Clearing condition] * Writing 1 Bit 8 is reserved. This bit is always read as 0. The write value should always be 0.
Only 1 can be written to clear the flag.
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Section 15 Controller Area Network (HCAN)
15.3.9
Receive Complete Register (RXPR)
RXPR is a 16-bit register containing status flags that indicate the normal reception of messages in mailboxes (buffers). For reception of a remote frame, when a bit in this register is set to 1, the corresponding remote request register (RFPR) bit is also set to 1 simultaneously.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: Bit Name RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 * Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* * Description When the message in mailbox n (n = 15 to 1) has been received error-free, RXPRn is set to 1. [Setting condition] * Completion of message (data frame or remote frame) reception in corresponding mailbox
[Clearing condition] Writing 1
Only 1 can be written to clear the flag.
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Section 15 Controller Area Network (HCAN)
15.3.10 Remote Request Register (RFPR) RFPR is a 16-bit register containing status flags that indicate normal reception of remote frames in mailboxes (buffers). When a bit in this register is set to 1, the corresponding receive complete register (RXPR) bit is also set to 1 simultaneously.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: Bit Name RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 * Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description When mailbox n (n = 15 to 0) has received the remote frame error-free, RFPRn (n = 15 to 1) is set to 1. [Setting condition] * Completion of remote frame reception in corresponding mailbox
[Clearing condition] * Writing 1
Only 1 can be written to clear the flag.
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Section 15 Controller Area Network (HCAN)
15.3.11
Interrupt Register (IRR)
IRR is a 16-bit interrupt status flag register.
Bit 15 Bit Name IRR7 Initial Value 0 R/W R/(W)* Description Overload Frame Interrupt Flag Status flag indicating on overload frame has been transmitted by HCAN. [Setting condition] * When an overload frame is transmitted in error active/passive state
[Clearing condition] * 14 IRR6 0 R/(W)* Writing 1 Bus Off Interrupt Flag Status flag indicating the bus off state caused by the transmit error counter. [Setting condition] * When TEC 256
[Clearing condition] * 13 IRR5 0 R/(W)* Writing 1 Error Passive Interrupt Flag Status flag indicating the error passive state caused by the transmit/receive error counter. [Setting condition] * When TEC 128 or REC 128
[Clearing condition] * Writing 1
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Section 15 Controller Area Network (HCAN) Bit 12 Bit Name IRR4 Initial Value 0 R/W R/(W)* Description Receive Overload Warning Interrupt Flag Status flag indicating the error warning state caused by the receive error counter. [Setting condition] * * 11 IRR3 0 R/(W)* When REC 96 Writing 1 [Clearing condition] Transmit Overload Warning Interrupt Flag Status flag indicating the error warning state caused by the transmit error counter. [Setting condition] * When TEC 96
[Clearing condition] * 10 IRR2 0 R Writing 1 Remote Frame Request Interrupt Flag Status flag indicating that a remote frame has been received in a mailbox (buffer), when MBIMR = 0. [Setting condition] * When remote frame reception is completed, when corresponding MBIMR = 0
[Clearing condition] * 9 IRR1 0 R Clearing of all bits in RFPR (remote request register)
Receive Message Interrupt Flag Status flag indicating that a mailbox (buffer) receive message has been received normally, when MBIMR = 0. [Setting condition] * When data frame or remote frame reception is completed, when corresponding MBIMR = 0
[Clearing condition] * Clearing of all bits in RXPR (receive complete register) Rev. 3.00 Oct 04, 2005 page 387 of 598 REJ09B0155-0300
Section 15 Controller Area Network (HCAN) Bit 8 Bit Name IRR0 Initial Value 1 R/W R/(W)* Description Reset Interrupt Flag Status flag indicating that the HCAN module has been reset. This bit cannot be masked by the interrupt mask register (IMR). If this bit is not cleared to 0 after entering power-on reset or returning from software standby mode, interrupt processing will start immediately when the interrupt controller enables interrupts. [Setting condition] * When the reset operation has finished after entering power-on reset or software standby mode
[Clearing condition] * 7 to 5 4 All 0 Writing 1 Reserved These bits are always read as 0. The write value should always be 0. IRR12 0 R/(W)* Bus Operation Interrupt Flag Status flag indicating detection of a dominant bit due to bus operation when the HCAN module is in HCAN sleep mode. [Setting condition] * Bus operation (dominant bit) detection in HCAN sleep mode
[Clearing condition] * 3, 2 All 0 Writing 1 Reserved These bits are always read as 0. The write value should always be 0.
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Section 15 Controller Area Network (HCAN) Bit 1 Bit Name IRR9 Initial Value 0 R/W R Description Unread Interrupt Flag Status flag indicating that a receive message has been overwritten before being read. [Setting condition] * When UMSR (unread message status register) is set
[Clearing condition] * 0 IRR8 0 R/(W)* Clearing of all bits in UMSR (unread message status register)
Mailbox Empty Interrupt Flag Status flag indicating that the next transmit message can be stored in the mailbox. [Setting condition] * When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort
[Clearing condition] * Note: * Only 1 can be written to clear the flag. Writing 1
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Section 15 Controller Area Network (HCAN)
15.3.12
Mailbox Interrupt Mask Register (MBIMR)
MBIMR is a 16-bit register that controls the enabling or disabling of individual mailbox (buffer) interrupt requests.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Mailbox Interrupt Mask (MBIMRx) When MBIMRn (n = 15 to 1) is cleared to 0, the interrupt request in mailbox n is enabled. When set to 1, the interrupt request is masked. The interrupt source in a transmit mailbox is TXPR clearing caused by transmission end or transmission cancellation. The interrupt source in a receive mailbox is RXPR setting on reception end.
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Section 15 Controller Area Network (HCAN)
15.3.13
Interrupt Mask Register (IMR)
IMR is a 16-bit register containing flags that enable or disable requests by individual interrupt sources. The reset interrupt flag cannot be masked.
Bit 15 Bit Name IMR7 Initial Value 1 R/W R/W Description Overload Frame Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR7 (OVR0) is enabled. When set to 1, it is masked. 14 IMR6 1 R/W Bus Off Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR6 (ERS0) is enabled. When set to 1, it is masked. 13 IMR5 1 R/W Error Passive Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR5 (ERS0) is enabled. When set to 1, it is masked. 12 IMR4 1 R/W Receive Overload Warning Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR4 (OVR0) is enabled. When set to 1, it is masked. 11 IMR3 1 R/W Transmit Overload Warning Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR3 (OVR0) is enabled. When set to 1, it is masked. 10 IMR2 1 R/W Remote Frame Request Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR2 (OVR0) is enabled. When set to 1, it is masked. 9 IMR1 1 R/W Receive Message Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR1 (RM1) is enabled. When set to 1, it is masked. 8 0 R Reserved This bit is always read as 0. The write value should always be 0.
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Section 15 Controller Area Network (HCAN) Bit 7 to 5 4 Bit Name Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 0. IMR12 1 R/W Bus Operation Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR12 (OVR0) is enabled. When set to 1, it is masked. 3, 2 All 1 R Reserved These bits are always read as 1. The write value should always be 0. 1 IMR9 1 R/W Unread Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR9 (OVR0) is enabled. When set to 1, it is masked. 0 IMR8 1 R/W Mailbox Empty Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR8 (SLE0) is enabled. When set to 1, it is masked.
15.3.14 Receive Error Counter (REC) The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating the number of receive message errors on the CAN bus. The count value is stipulated in the CAN protocol. 15.3.15 Transmit Error Counter (TEC) The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter indicating the number of transmit message errors on the CAN bus. The count value is stipulated in the CAN protocol.
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Section 15 Controller Area Network (HCAN)
15.3.16
Unread Message Status Register (UMSR)
UMSR is a 16-bit register containing status flags that indicate, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. When overwritten by a new message, data in the unread receive message is lost.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: Bit Name UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 * Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description The received message has been overwritten by a new message before being read. [Setting condition] * When a new message is received before RXPR is cleared Writing 1
[Clearing condition] *
Only 1 can be written to clear the flag.
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Section 15 Controller Area Network (HCAN)
15.3.17 Local Acceptance Filter Masks (LAFML, LAFMH) LAFML and LAFMH are 16-bit registers that individually set the identifier bits of the message to be stored in mailbox 0 as Don't Care. For details, refer to section 15.4.4, Message Reception. The relationship between the identifier bits and mask bits are shown in the following. * LAFML
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, ID-7 of the receive message identifier is not compared. When this bit is set to 1, ID-6 of the receive message identifier is not compared. When this bit is set to 1, ID-5 of the receive message identifier is not compared. When this bit is set to 1, ID-4 of the receive message identifier is not compared. When this bit is set to 1, ID-3 of the receive message identifier is not compared. When this bit is set to 1, ID-2 of the receive message identifier is not compared. When this bit is set to 1, ID-1 of the receive message identifier is not compared. When this bit is set to 1, ID-0 of the receive message identifier is not compared. When this bit is set to 1, ID-15 of the receive message identifier is not compared. When this bit is set to 1, ID-14 of the receive message identifier is not compared. When this bit is set to 1, ID-13 of the receive message identifier is not compared. When this bit is set to 1, ID-12 of the receive message identifier is not compared. When this bit is set to 1, ID-11 of the receive message identifier is not compared. When this bit is set to 1, ID-10 of the receive message identifier is not compared. When this bit is set to 1, ID-9 of the receive message identifier is not compared. When this bit is set to 1, ID-8 of the receive message identifier is not compared.
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Section 15 Controller Area Network (HCAN)
* LAFMH
Bit 15 14 13 Bit Name LAFMH7 LAFMH6 LAFMH5 Initial Value 0 0 0 All 0 R/W R/W R/W R/W R Description When this bit is set to 1, ID-20 of the receive message identifier is not compared. When this bit is set to 1, ID-19 of the receive message identifier is not compared. When this bit is set to 1, ID-18 of the receive message identifier is not compared. Reserved These bits are always read as 0. The write value should always be 0. 9 8 7 6 5 4 3 2 1 0 LAFMH1 LAFMH0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When this bit is set to 1, ID-17 of the receive message identifier is not compared. When this bit is set to 1, ID-16 of the receive message identifier is not compared. When this bit is set to 1, ID-28 of the receive message identifier is not compared. When this bit is set to 1, ID-27 of the receive message identifier is not compared. When this bit is set to 1, ID-26 of the receive message identifier is not compared. When this bit is set to 1, ID-25 of the receive message identifier is not compared. When this bit is set to 1, ID-24 of the receive message identifier is not compared. When this bit is set to 1, ID-23 of the receive message identifier is not compared. When this bit is set to 1, ID-22 of the receive message identifier is not compared. When this bit is set to 1, ID-21 of the receive message identifier is not compared.
12 to 10
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Section 15 Controller Area Network (HCAN)
15.3.18 Message Control (MC15 to MC0) The message control register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message control registers are in RAM, their initial values after power-on are undefined. Be sure to initialize them by writing 1 or 0. Figure 15.2 shows the register names for each mailbox.
Mail box 0 Mail box 1 Mail box 2 Mail box 3
MC0[1] MC1[1] MC2[1] MC3[1]
MC0[2] MC1[2] MC2[2] MC3[2]
MC0[3] MC1[3] MC2[3] MC3[3]
MC0[4] MC1[4] MC2[4] MC3[4]
MC0[5] MC1[5] MC2[5] MC3[5]
MC0[6] MC1[6] MC2[6] MC3[6]
MC0[7] MC1[7] MC2[7] MC3[7]
MC0[8] MC1[8] MC2[8] MC3[8]
Mail box 15
MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8]
Figure 15.2 Message Control Register Configuration The setting of message control registers are shown in the following. Figures 15.3 and 15.4 show the correspondence between the identifiers and register bit names.
SOF
ID-28 ID-27 identifier
ID-18
RTR
IDE
R0
Figure 15.3 Standard Format
SOF
ID-28 ID-27
ID-18
SRR
IDE
ID-17 ID-16 Extended identifier
ID-0
RTR
R1
Standard identifier
Figure 15.4 Extended Format
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Section 15 Controller Area Network (HCAN) Register Name MCx[1]
Bit 7 to 4 3 to 0
Bit Name
R/W R/W
Description The initial value of these bits is undefined. They must be initialized by writing 0 or 1. Data Length Code Set the data length of a data frame or the data length requested in a remote frame within the range of 0 to 8 bits. 0000: 0 bytes 0001: 1 byte 0010: 2 bytes 0011: 3 bytes 0100: 4 bytes 0101: 5 bytes 0110: 6 bytes 0111: 7 bytes 1***: 8 bytes
DLC3 to DLC0 R/W
MCx[2] MCx[3] MCx[4] MCx[5]
7 to 0 7 to 0 7 to 0 7 to 5 4
ID-20 to ID-18 RTR
R/W R/W R/W R/W R/W
The initial value of these bits is undefined; they must be initialized by writing 0 or 1.
Sets ID-20 to ID-18 in the identifier. Remote Transmission Request Used to distinguish between data frames and remote frames. 0: Data frame 1: Remote frame
3
IDE
R/W
Identifier Extension Used to distinguish between the standard format and extended format of data frames and remote frames. 0: Standard format 1: Extended format
2 1 to 0 MCx[6] MCx[7] MCx[8] 7 to 0 7 to 0 7 to 0
ID-17 to ID-16 ID-28 to ID-21 ID-7 to ID-0 ID-15 to ID-8
R/W R/W R/W R/W R/W
The initial value of this bit is undefined. It must be initialized by writing 0 or 1. Sets ID-17 and ID-16 in the identifier. Sets ID-28 to ID-21 in the identifier. Sets ID-7 to ID-0 in the identifier. Sets ID-15 to ID-8 in the identifier.
Note: x: Mailbox number Rev. 3.00 Oct 04, 2005 page 397 of 598 REJ09B0155-0300
Section 15 Controller Area Network (HCAN)
15.3.19 Message Data (MD15 to MD0) The message data register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message data registers are in RAM, their initial values after poweron are undefined. Be sure to initialize them by writing 1 or 0. Figure 15.5 shows the register names for each mailbox.
Mail box 0 Mail box 1 Mail box 2 Mail box 3
MD0[1] MD1[1] MD2[1] MD3[1]
MD0[2] MD1[2] MD2[2] MD3[2]
MD0[3] MD1[3] MD2[3] MD3[3]
MD0[4] MD1[4] MD2[4] MD3[4]
MD0[5] MD1[5] MD2[5] MD3[5]
MD0[6] MD1[6] MD2[6] MD3[6]
MD0[7] MD1[7] MD2[7] MD3[7]
MD0[8] MD1[8] MD2[8] MD3[8]
Mail box 15
MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8]
Figure 15.5 Message Data Configuration
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Section 15 Controller Area Network (HCAN)
15.3.20
HCAN Monitor Register (HCANMON)
HCANMON is an 8-bit register that enables/disables an HCAN receive interrupt, controls transmission stop of the HTxD pin, and reflects the states of the HCAN pins.
Bit 7 Bit Name RxDIE Initial Value 0 R/W R/W Description HRxD Interrupt Enable
2QRI
Selects whether an PF0 or HRxD pin. 1: An 6 TxSTP 0 R/W
2QRI
interrupt is caused by
0: An
interrupt is caused by pin PF0 interrupt is caused by the HRxD pin
HTxD Transmission Stop Controls transmission stop of the HTxD pin. 0: Enables transmission from the HTxD pin 1: Fixes an output level of the HTxD pin at 1 and transmission is stopped
5 to 2
Undefined
Reserved These bits are always read as undefined values and cannot be modified.
1
TxD
Undefined
R
Transmission pin The state of the HTxD pin is read. This bit cannot be modified.
0
RxD
Undefined
R
Reception pin The state of the HRxD pin is read. This bit cannot be modified.
2QRI
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Section 15 Controller Area Network (HCAN)
15.4
15.4.1
Operation
Hardware and Software Resets
The HCAN can be reset by a hardware reset or software reset. * Hardware Reset At power-on reset, or in hardware or software standby mode, the HCAN is initialized by automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR. At the same time, all internal registers, except for message control and message data registers, are initialized by a hardware reset. * Software Reset The HCAN can be reset by setting the MCR reset request bit (MCR0) in MCR via software. In a software reset, the error counters (TEC and REC) are initialized, however other registers are not. If the MCR0 bit is set while the CAN controller is performing a communication operation (transmission or reception), the initialization state is not entered until message transfer has been completed. The reset status bit (GSR3) in GSR is set on completion of initialization. 15.4.2 Initialization after Hardware Reset
After a hardware reset, the following initialization processing should be carried out: 1. 2. 3. 4. 5. Clearing of IRR0 bit in the interrupt register (IRR) Bit rate setting Mailbox transmit/receive settings Mailbox (RAM) initialization Message transmission method setting
These initial settings must be made while the HCAN is in bit configuration mode. Configuration mode is a state in which the GSR3 bit in GSR is set to 1 by a reset. Configuration mode is exited by clearing the MCR0 bit in MCR to 0; when the MCR0 bit is cleared to 0, the HCAN automatically clears the GSR3 bit in GSR. There is a delay between clearing the MCR0 bit and clearing the GSR3 bit because the HCAN needs time to be internally reset. After the HCAN exits configuration mode, the power-up sequence begins, and communication with the CAN bus is possible as soon as 11 consecutive recessive bits have been detected.
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IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. Since an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared.
Hardware reset
: Settings by user : Processing by hardware
MCR0 = 1 (automatic)
IRR0 = 1 (automatic) GSR3 = 1 (automatic)
Initialization of HCAN module
Clear IRR0 BCR setting MBCR setting Mailbox initialization Message transmission method initialization
Bit configuration mode Period in which BCR, MBCR, etc., are initialized
MCR0 = 0
GSR3 = 0? Yes IMR setting (interrupt mask setting) MBIMR setting (interrupt mask setting) MC[x] setting (receive identifier setting) LAFM setting (receive identifier mask setting)
No
GSR3 = 0 & 11 recessive bits received? Yes
No
Can bus communication enabled
Figure 15.6 Hardware Reset Flowchart
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MCR0 = 1 : Settings by user Bus idle? Yes GSR3 = 1 (automatic) Yes Initialization of REC and TEC only No : Processing by hardware
BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization OK? Yes
Correction No
GSR3 = 1? Yes MCR0 = 0
No
GSR3 = 0? Yes
No
Correction IMR setting MBIMR setting MC[x] setting LAFM setting OK?
No
Yes
GSR3 = 0 & 11 recessive bits received?
No
Yes CAN bus communication enabled
Figure 15.7 Software Reset Flowchart
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Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit configuration register (BCR). Settings should be made such that all CAN controllers connected to the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the settable time quanta (tq).
1-bit time (25 to 8 time quanta)
SYNC_SEG
PRSEG
PHSEG1
PHSEG2 Time segment 2 (TSEG2) 2 to 8 time quanta
Time segment 1 (TSEG1) 1 time quanta 4 to 16 time quanta
Figure 15.8 Detailed Description of One Bit SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer segment for correcting phase drift (negative). This segment is shortened when synchronization (resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, BSP, and SJW) are shown in table 15.2. Table 15.2 Limits for the Settable Value
Name Time segment 1 Time segment 2 Baud rate prescaler Bit sample point Re-synchronization jump width Abbreviation TSEG1 TSEG2 BRP BSP SJW *1 Min. Value B'0011 B'001*3 *2 Max. Value B'1111 B'111 B'111111 B'1 B'11
B'000000 B'0 B'00
Notes: 1. SJW is stipulated in the CAN specifications: 3 SJW 0 2. The minimum value of TSEG2 is stipulated in the CAN specifications: TSEG2 SJW 3. The minimum value of TSEG1 is stipulated in the CAN specifications: TSEG1 > TSEG2
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Time quanta (tq) is an integer multiple of the number of system clocks, and is determined by the baud rate prescaler (BRP) as follows. fCLK is the system clock frequency. tq = 2 x (BPR setting + 1)/fCLK The following formula is used to calculate the 1-bit time and bit rate. 1-bit time = tq x (3 + TSEG1 + TSEG2) Bit rate = 1/Bit time = fCLK/{2 x (BPR setting + 1) x (3 + TSEG1 + TSEG2)} Note: fCLK = (system clock) A BCR value is used for BRP, TSEG1, and TSEG2.
Example: With a system clock of 24 MHz, a BRP setting of B'000000, a TSEG1 setting of B'0101, and a TSEG2 setting of B'100: Bit rate = 24/{2 x (0 + 1) x (3 + 5 + 4)} = 1 Mbps Table 15.3 Setting Range for TSEG1 and TSEG2 in BCR
TSEG2 (BCR14 to BCR12) 001 TSEG1 (BCR11 to BCR8) 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 No Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* Yes* 010 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 011 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 100 No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 101 No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 110 No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes 111 No No No No No Yes Yes Yes Yes Yes Yes Yes Yes
Note: The time quantum values for TSEG1 and TSEG2 are determined by TSEG value + 1. * Settable when bits BRP is not B'000000.
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Mailbox Transmit/Receive Settings: The HCAN has 16 mailboxes. Mailbox 0 is receive-only, while mailboxes 15 to 1 can be set for transmission or reception. The initial status of mailboxes 15 to 1 is for transmission. Mailbox transmit/receive settings are not initialized by a software reset. Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding mailbox for transmission use, whereas a setting of 1 in MBCR designates the corresponding mailbox for reception use. When setting mailboxes for reception, in order to improve message reception efficiency, high-priority messages should be set in low-to-high mailbox order. Mailbox (Message Control/Data) Initial Settings: Message control/data are held in RAM, and so their initial values are undefined after power is supplied. Initial values must therefore be set in all the mailboxes (by writing 0s or 1s). Setting the Message Transmission Method: The following two kinds of message transmission methods are available. * Transmission order determined by message identifier priority * Transmission order determined by mailbox number priority Either of the message transmission methods can be selected with the message transmission method bit (MCR2) in the master control register (MCR): When messages are set to be transmitted according to the message identifier priority, if several messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority in the message identifier is stored in the transmit buffer. CAN bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. When the TXPR bit is set, the highest-priority message is found and stored in the transmit buffer. When messages are set to be transmitted according to the mailbox number priority, if several messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order. CAN bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. 15.4.3 Message Transmission
Messages are transmitted using mailboxes 15 to 1. The transmission procedure after initial settings is described below, and a transmission flowchart is shown in figure 15.9.
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Initialization (after hardware reset only) Clear IRR0 BCR setting MBCR setting Mailbox initialization Message transmission method setting Interrupt settings Transmit data setting Arbitration field setting Control field setting Data field setting
: Settings by user : Processing by hardware
Message transmission wait TXPR setting
Bus idle?
No
Yes Message transmission GSR2 = 0 (during transmission only)
Transmission completed?
No
Yes TXACK = 1 IRR8 = 1
IMR8 = 1?
Yes
No Interrupt to CPU Clear TXACK Clear IRR8
End of transmission
Figure 15.9 Transmission Flowchart CPU Interrupt Source Settings: The CPU interrupt source is set by the interrupt mask register (IMR) and mailbox interrupt mask register (MBIMR). Transmission acknowledge and
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transmission abort acknowledge interrupts can be generated for individual mailboxes in the mailbox interrupt mask register (MBIMR). Arbitration Field Setting: The arbitration field is set by the message control registers MCx[8] to MCx[5] in a transmit mailbox. For a standard format, an 11-bit identifier (ID-28 to ID-18) and the RTR bit are set, and the IDE bit is cleared to 0. For an extended format, a 29-bit identifier (ID-28 to ID-0) and the RTR bit are set, and the IDE bit is set to 1. Control Field Setting: In the control field, the byte length of the data to be transmitted is set within the range of zero to eight bytes. The register to be set is the message control register MCx[1] in a transmit mailbox. Data Field Setting: In the data field, the data to be transmitted is set within the range zero to eight. The registers to be set are the message data registers MDx[8] to MDx[1]. The byte length of the data to be transmitted is determined by the data length code in the control field. Even if data exceeding the value set in the control field is set in the data field, up to the byte length set in the control field will actually be transmitted. Message Transmission: If the corresponding mailbox transmit wait bit (TXPR15 to TXPR1) in the transmit wait register (TXPR) is set to 1 after message control and message data registers have been set, the message enters transmit wait state. If the message is transmitted error-free, the corresponding acknowledge bit (TXACK15 to TXACK1) in the transmit acknowledge register (TXACK) is set to 1, and the corresponding transmit wait bit (TXPR15 to TXPR1) in the transmit wait register (TXPR) is automatically cleared to 0. Also, if the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU. If transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: * CAN bus arbitration failure (failure to acquire the bus) * Error during transmission (bit error, stuff error, CRC error, frame error, or ACK error) Message Transmission Cancellation: Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the bit for the corresponding mailbox (TXCR15 to TXCR1) to 1 in the transmit cancel register (TXCR). Clearing the transmit wait register (TXPR) does not cancel transmission. When cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (ABACK), and then an interrupt to the CPU can be requested. Also, if the corresponding bit (MBIMR15 to MBIMR1) in the mailbox
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interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU. However, a transmit wait message cannot be canceled at the following times: * During internal arbitration or CAN bus arbitration * During data frame or remote frame transmission Figure 15.10 shows a flowchart for transmit message cancellation.
Message transmit wait TXPR setting
: Settings by user : Processing by hardware
Set TXCR bit corresponding to message to be canceled
Cancellation possible?
No
Yes Message not sent Clear TXCR, TXPR ABACK = 1 IRR8 = 1 Completion of message transmission TXACK = 1 Clear TXCR, TXPR IRR8 = 1
IMR8 = 1?
Yes
No Interrupt to CPU
Clear TXACK Clear ABACK Clear IRR8
End of transmission/transmission cancellation
Figure 15.10 Transmit Message Cancellation Flowchart
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15.4.4
Message Reception
The reception procedure after initial settings is described below. A reception flowchart is shown in Figure 15.11.
Initialization Clear IRR0 BCR setting MBCR setting Mailbox (RAM) initialization Interrupt settings Receive data setting Arbitration field setting Local acceptance filter settings
: Settings by user : Processing by hardware
Message reception (Match of identifier in mailbox?) Yes
No
Same RXPR = 1? No
Yes Unread message
Data frame? Yes RXPR IRR1 = 1
No
RXPR, RFPR = 1 IRR2 = 1, IRR1 = 1
Yes IMR1 = 1? No Interrupt to CPU Message control read Message data read
IMR2 = 1? No Interrupt to CPU Message control read Message data read
Yes
Clear IRR1
Clear IRR2, IRR1 Transmission of data frame corresponding to remote frame
End of reception
Figure 15.11 Reception Flowchart
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CPU Interrupt Source Settings: CPU interrupt source settings are made in the interrupt mask register (IMR) and mailbox interrupt register (MBIMR). The message to be received is also specified. Data frame and remote frame receive wait interrupt requests can be generated for individual mailboxes in the MBIMR. Arbitration Field Setting: To receive a message, the message identifier must be set in advance in the message control registers (MCx[8] to MCx[1]) for the receiving mailbox. When a message is received, all the bits in the receive message identifier are compared with those in each message control register identifier, and if a complete match is found, the message is stored in the matching mailbox. Mailbox 0 has a local acceptance filter mask (LAFM) that allows Don't Care settings. The LAFM setting can be made only for mailbox 0. By setting the Don't Care for all the bits in the receive message identifier, messages of multiple identifiers can be received. Examples: * When the identifier of mailbox 1 is 010_1010_1010 (standard format), only one kind of message identifier can be received by mailbox 1: Identifier 1: 010_1010_1010 * When the identifier of mailbox 0 is 010_1010_1010 (standard format) and the LAFM setting is 000_0000_0011 (0: Care, 1: Don't Care), a total of four kinds of message identifiers can be received by mailbox 0: Identifier 1: 010_1010_1000 Identifier 2: 010_1010_1001 Identifier 3: 010_1010_1010 Identifier 4: 010_1010_1011 Message Reception: When a message is received, a CRC check is performed automatically. If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether the message can be received or not. * Data frame reception If the received message is confirmed to be error-free by the CRC check, the identifier in the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive message are compared. If a complete match is found, the message is stored in the matching mailbox. The message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (RXPR15 to RXPR0) in the receive complete register (RXPR) is set. However, if the identifier matches that of mailbox 0 LAFM, the mailbox comparison sequence does not end at that point, but continues from mailbox 1. Therefore, the message for mailbox 0
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can also be received by another mailbox. Note that the same message cannot be stored in two or more mailbox of the mailboxes 15 to 1. On receiving a message, a CPU interrupt request may be generated according to the settings of the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). * Remote frame reception A mailbox can store two kinds of messages: data frames and remote frames. A remote frame differs from a data frame in the value of the remote transmission request bit (RTR) in the message control register and its 0-byte data field. The data length to be returned in a data frame must be stored in the data length code (DLC) in the message control. When a remote frame (RTR = recessive) is received, the corresponding bit in the remote request wait register (RFPR) is set. Interrupts can be sent to the CPU according to the settings of the corresponding bit (MBIMR15 to MBIMR0) in the mailbox interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register (IMR). Unread Message Overwrite: If the receive message identifier matches the mailbox identifier, the receive message is stored in the mailbox regardless of whether the mailbox contains an unread message or not. If a message overwrite occurs, the corresponding bit (UMSR15 to UMSR0) in the unread message register (UMSR) is set. In overwriting an unread message, the unread message register (UMSR) is set when a new message is received before the corresponding bit in the receive complete register (RXPR) has been cleared. If the unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to enable interrupts at this time, an interrupt can be sent to the CPU. Figure 15.12 shows a flowchart for unread message overwriting.
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Unread message overwrite
: Settings by user : Processing by hardware
UMSR = 1 IRR9 = 1
IMR9 = 1?
Yes
No Interrupt to CPU
Clear IRR9 Message control/message data read
End
Figure 15.12 Unread Message Overwrite Flowchart 15.4.5 HCAN Sleep Mode
The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state in order to reduce current consumption. Figure 15.13 shows a flowchart of the HCAN sleep mode.
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MCR5 = 1 : Settings by user : Processing by hardware Bus idle? No
Yes Initialize TEC and REC
Bus operation? Yes IRR12 = 1
No
MB should not be accessed. IMR12 = 1? No CPU interrupt Yes
Sleep mode clearing method MCR7 = 0? Yes (manual)
No (automatic)
Clear sleep mode?
No
Yes GSR3 = 1? No
Yes MCR5 = 0
GSR3 = 1?
No
Yes MCR5 = 0
11 recessive bits received? Yes CAN bus communication possible
No
Figure 15.13 HCAN Sleep Mode Flowchart
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HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected: * Clearing by software * Clearing by CAN bus operation In order to re-enter CAN bus communication enabled state, eleven recessive bits must be received after HCAN sleep mode was cleared. Clearing by Software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU. Clearing by CAN Bus Operation: The cancellation method is selected by the MCR7 bit setting in MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs an operation and this change is detected. In this case, the first message is not stored in a mailbox; messages will be received normally from the second message onward. When a change is detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is set to enable interrupts at this time, an interrupt can be sent to the CPU.
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15.4.6
HCAN Halt Mode
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 15.14 shows a flowchart of the HCAN halt mode.
MCR1 = 1
Bus idle?
No
Yes Set MBCR
MCR1 = 0
: Settings by user CAN bus communication possible : Processing by hardware
Figure 15.14 HCAN Halt Mode Flowchart HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until the bus becomes idle. HCAN halt mode is cleared by clearing MCR1 to 0.
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15.5
Interrupt Sources
Table 15.4 lists the HCAN interrupt sources. These sources can be masked except the reset processing interrupt by power-on reset (IRR0). Masking is implemented using the mailbox interrupt mask register (MBIMR), interrupt mask register (IMR), and IRQ enable register (IER). For details on the interrupt vector of each interrupt source, refer to section 5, Interrupt Controller. Table 15.4 HCAN Interrupt Sources
Name ERS0/OVR0 Description Error passive interrupt (TEC 128 or REC 128) Bus off interrupt (TEC 256) Reset processing interrupt by power-on reset Remote frame reception Error warning interrupt (TEC 96) Error warning interrupt (REC 96) Overload frame transmission interrupt Unread message overwrite Detection of CAN bus operation in HCAN sleep mode RM0 RM1 SLE0 IRQ2 Mailbox 0 message reception Mailbox 15 to 1 message reception Message transmission/transmit cancellation Setting the RxDIE bit in HCANMON to 1 generates an IRQ2 interrupt caused by an HRxD input signal. Interrupt Flag IRR5 IRR6 IRR0 IRR2 IRR3 IRR4 IRR7 IRR9 IRR12 IRR1 IRR1 IRR8 IRQ2F Possible Not possible Not possible Possible DTC Activation Not possible
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15.6
DTC Interface
The DTC can be activated by the reception of a message in HCAN mailbox 0. When the DTC activation is set and DTC transfer ends, the RXPR0 and RFPR0 flags are automatically cleared. An interrupt request is not sent to the CPU by a reception interrupt from the HCAN. Figure 15.15 shows a DTC transfer flowchart.
: Settings by user DTC initialization DTC enable register setting DTC register information setting : Processing by hardware
Message reception in HCAN's mailbox 0
DTC activation
End of DTC transfer?
No
Yes
RXPR and RFPR clearing
Transfer counter = 0 or DISEL = 1? Yes Interrupt to CPU
No
End
Figure 15.15 DTC Transfer Flowchart
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Section 15 Controller Area Network (HCAN)
15.7
CAN Bus Interface
A bus transceiver IC is necessary to connect the H8S/2628 Group to a CAN bus. A Philips PCA82C250 transceiver IC is recommended. If any other product is used, confirm that it is compatible with the PCA82C250. Figure 15.16 shows a sample connection diagram.
124 Vcc PCA82C250 RS HRxD HTxD NC 124 Note: NC: No connection Vcc CAN bus
This LSI
RxD CANH TxD CANL Vref GND
Figure 15.16 High-Speed Interface Using PCA82C250
15.8
15.8.1
Usage Notes
Module Stop Mode Setting
HCAN operation can be disabled or enabled using the module stop control register. The HCAN operation is set to be halted initially. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes. 15.8.2 Reset
The HCAN is reset by a power-on reset, in hardware standby mode, and in software standby mode. All the registers are initialized by a reset, however mailboxes (message control (MCx[x])/message data (MDx[x])) are not initialized. Mailboxes (message control (MCx[x])/message data (MDx[x])) are initialized after power-on and at this time, their initial values are undefined. Therefore, always initialize mailboxes after a power-on reset, a transition to hardware standby mode, or software standby mode. After a power-on reset or recovery from software standby mode, the reset interrupt flag (IRR0) is automatically set. Since this bit cannot be masked in the interrupt mask register (IMR), an HCAN interrupt will be initiated immediately
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after an HCAN interrupt is enabled by the interrupt controller without clearing the flag. IRR0 should therefore be cleared at initialization. 15.8.3 HCAN Sleep Mode
The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set even in sleep mode. 15.8.4 Interrupts
When the mailbox interrupt mask register (MBIMR) is set, the interrupt registers (IRR8, 2, 1) are not set by reception completion, transmission completion, or transmission cancellation of the set mailboxes. 15.8.5 Error Counters
In the case of error active and error passive, REC and TEC perform count up and down normally. In the bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. When REC reaches 96 during the count, IRR4 and GSR1 are set. 15.8.6 Register Access
Byte or word access can be performed for all HCAN registers. Longword access should be avoided. 15.8.7 HCAN Medium-Speed Mode
In medium-speed mode, the HCAN registers cannot be read/written. 15.8.8 Register Hold in Standby Modes
All HCAN registers are initialized in hardware standby mode and software standby mode. 15.8.9 Use on Bit Manipulation Instructions
Since the HCAN status flag is cleared by writing 1, do not use the bit manipulation instructions to clear the flag. To clear the flag, use the MOV instructions and write 1 only to the bit to be cleared.
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15.8.10 HCAN TXCR Operation 1. When the transmit wait cancel register (TXCR) is used to cancel a transmit wait message in a transmit wait mailbox, the corresponding bit to TXCR and the transmit wait register (TXPR) may not be cleared even if transmission is canceled. This occurs when the following conditions are all satisfied. Conditions: * The HRxD pin is stacked to 1 because of a CAN bus error, etc. * There is at least one mailbox waiting for transmission or being transmitted. * The message transmission in a mailbox being transmitted is canceled by TXCR. If this occurs, transmission is canceled. However, since TXPR and TXCR states are indicated wrongly that a message is being cancelled, transmission cannot be restarted even if the stack state of the HRxD pin is canceled and the CAN bus recovers the normal state. If there are at least two transmission messages, a message which is not being transmitted is canceled and a message being transmitted retains its state. To avoid this, one of the following countermeasures must be executed. Countermeasures: * Transmission must not be canceled by TXCR. When transmission is normally completed after the CAN bus has recovered, TXPR is cleared and the HCAN recovers the normal state. * To cancel transmission, the corresponding bit to TXCR must be written to 1 continuously until the bit becomes 0. TXPR and TXCR are cleared and the HCAN recovers the normal state. 2. When the bus-off state is entered while TXPR is set and the transmit wait state is entered, the internal state machine does not operate even if TXCR is set during the bus-off state. Therefore transmission cannot be canceled. The message can be canceled when one message is transmitted or a transmission error occurs after the bus-off state is recovered. To clear a message after the bus-off state is recovered, the following countermeasure must be executed. Countermeasure: * A transmit wait message must be cleared by resetting the HCAN during the bus-off period. To reset the HCAN, the module stop bit (MSTPC3 in MSTPCRC) must be set or cleared. In this case, the HCAN is entirely reset. Therefore the initial settings must be made again.
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15.8.11 HCAN Transmit Procedure When transmission is set while the bus is in the idle state, if the next transmission is set or the set transmission is canceled under the following conditions within 50 s, the transmit message ID of being set may be damaged. * When the second transmission has the message whose priority is higher than the first one. * When the massage of the highest priority is canceled in the first transmission. Make whichever setting shown below to avoid the message IDs from being damaged. * Set transmission in one TXPR. After transmission of all transmit messages is completed, set transmission again (mass transmission setting). The interval between transmission settings should be 50 s or longer. * Make the transmission setting according to the priority of transmit messages. * Set the interval to be 50 s or longer between TXPR and another TXPR or between TXPR and TXCR. Table 15.5 Interval Limitation between TXPR and TXPR or between TXPR and TXCR
Baud Rate (bps) 1M 500 k 250 k Set Interval (s) 50 50 50
15.8.12 Canceling HCAN Reset and HCAN Sleep Mode Before canceling the software reset for HCAN or HCAN sleep mode (MCR0 = 0 or MCR5 = 0), confirm that the reset status bit (GSR3) is set to 1. 15.8.13 Accessing Mailbox in HCAN Sleep Mode The mailboxes should not be accessed in HCAN sleep mode. If mailboxes are accessed in HCAN sleep mode, the CPU may stop. When registers are accessed in HCAN sleep mode, the CPU does not stop. When mailboxes are accessed in modes other than HCAN sleep mode, the CPU does not stop.
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Section 16 Synchronous Serial Communication Unit (SSU)
Section 16 Synchronous Serial Communication Unit (SSU)
This LSI has two independent synchronous serial communication unit (SSU) channels. The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication. Synchronous serial communication can be performed with devices having different clock polarity and clock phase. Figure 16.1 is a block diagram of the SSU.
16.1
* * * * *
Features
* * * *
*
Choice of master mode or slave mode Choice of standard mode or bidirectional mode Synchronous serial communication with devices with different clock polarity and clock phase Choice of 8/16/32-bit width of transmit/receive data Full-duplex communication capability The shift register is incorporated, enabling transmission and reception to be executed simultaneously. Continuous serial communication Choice of LSB-first or MSB-first transfer Choice of a clock source /2, /4, /8, /16, /32, /64, /128, /256, or external clock Five interrupt sources transmit-end, transmit-data-register-empty, receive-data-register-full, overrun-error, and conflict error Module stop mode can be set
SCISSU0A_000120020900
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Section 16 Synchronous Serial Communication Unit (SSU)
Figure 16.1 shows a block diagram of the SSU.
Module data bus
Bus interface
Internal data bus
SSCRH SSTDR 0 SSTDR 1 SSTDR 2 SSTDR 3 SSRDR 0 SSRDR 1 SSRDR 2 SSRDR 3 SSCRL SSMR SSER SSSR Control circuit OEI CEI RXI TXI TEI
SSTRSR
Shift-out
Clock Clock selector
/2 /4 /8 /16 /32 /64 /128 /256
Selector
Shift-in
SSI
SSO
SCS
SSCK (External clock)
Legend: SSCRH: SSCRL: SSMR: SSER: SSSR: SSTDR3 to SSTDR0: SSRDR3 to SSRDR0: SSTRSR:
SS control register H SS control register L SS mode register SS enable register SS status register SS transmit data register SS receive data register SS transmit/recive shift register
Figure 16.1 Block Diagram of SSU
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Section 16 Synchronous Serial Communication Unit (SSU)
16.2
Input/Output Pins
Table 16.1 shows the SSU pin configuration. Table 16.1 Pin Configuration
Name SSU clock SSU receive data input SSU transmit data output SSU chip select input/output Symbol SSCK SSI SSO I/O I/O I/O I/O I/O Function SSU clock input/output SSU receive data input/output SSU transmit data input/output SSU chip select input/output
16.3
Register Descriptions
The SSU has the following registers. * * * * * * * SS control register H (SSCRH) SS control register L (SSCRL) SS mode register (SSMR) SS enable register (SSER) SS status register (SSSR) SS transmit data register 3 to 0 (SSTDR3 to SSTDR0) SS receive data register 3 to 0 (SSRDR3 to SSRDR0)
SCS
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Section 16 Synchronous Serial Communication Unit (SSU)
16.3.1
SS Control Register H (SSCRH)
SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value pin selection. selection, SSCK pin selection, and
Bit 7 Bit Name MSS Initial Value 0
6
BIDE
0
5 4
SOL
0 0
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SCS
R/W R/W
Description Master/Slave Device Selection Selects that this module is used in master mode or slave mode. When master mode is selected, transfer clocks are output from the SSCK pin. When the CE bit in SSSR is set, this bit is automatically cleared. 0: Slave mode is selected 1: Master mode is selected
R/W
Bidirectional Mode Enable Selects that both serial data input pin and output pin are used or one of them is used. However, transmission and reception are not performed simultaneously when bidirectional mode is selected. For details, section 16.4.3, Relationship between Data I/O Pins and Shift Register. 0: Standard mode (two pins are used as data input and output) 1: Bidirectional mode (one pin is used for data input and output)
R/W
Reserved The write value should always be 0. Serial Data Output Value Selection The output level of serial data, which retains that of the last bit, can be modified by operating this bit before or after transmission. When modifying the output level, use the MOV instruction after clearing the SOLP bit to 0. Since writing to this bit during data transmission causes malfunctions, this bit should not be modified. 0: Serial data output is modified to low level 1: Serial data output is modified to high level
Section 16 Synchronous Serial Communication Unit (SSU) Bit 3 Bit Name SOLP Initial Value 1 R/W R/W Description SOL Bit Write Protect When modifying the output level of serial data, use the MOV instruction after setting SOL to 1 and clearing SOLP to 0, or by clearing SOL and SOLP to 0. 0: Output level can be modified by the SOL value 1: Output level cannot be modified by the SOL value. This bit is always read as 1 2 SCKS 0 R/W SSCK Pin Selection Selects that the SSCK pin functions as a port or a serial clock pin. When MSS = 1, the SSCK pin functions as a serial clock output pin regardless of the setting of this bit. 0: Functions as an I/O port 1: Functions as a serial clock 0 CSS0 0 R/W Select that the pin functions as a port or input or output. However, when MSS = 0, the pin functions as an input pin regardless of the CSS1 and CSS0 settings. 00: I/O port 10: Functions as automatic input/output (however, functions as input before and after transfer and outputs a low level during transfer) 11: Functions as automatic output (however, outputs a high level before and after transfer and outputs a low level during transfer) 01: Functions as 1 CSS1 0 R/W Pin Selection
input
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SCS SCS
SCS
SCS SCS
SCS
SCS
SCS
Section 16 Synchronous Serial Communication Unit (SSU)
16.3.2
SS Control Register L (SSCRL)
SSCRL selects software reset and transmit/receive data width.
Bit 7, 6 5 Bit Name SRES Initial Value All 0 0 R/W R/W Description Reserved The write value should always be 0. Software Reset Setting this bit to 1 forcibly resets the SSU internal sequencer. After that, this bit is automatically cleared. The ORER, TEND, TDRE, RDRF, and CE bits in SSSR and the TE and RE bits in SSER are also initialized. Values of other bits for SSU registers are held. To stop transfer, set this bit to 1 to reset the SSU internal sequencer. 4 to 2 1 0 DATS1 DATS0 All 0 0 0 R/W R/W Reserved The write value should always be 0. Transmit/Receive Data Length Selection Select serial data length from 8, 16, and 32 bits. 00: 8 bits 01: 16 bits 10: 32 bits 11: Setting invalid
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Section 16 Synchronous Serial Communication Unit (SSU)
16.3.3
SS Mode Register (SSMR)
SSMR selects the MSB first/LSB first, clock phase, clock polarity, and clock rate of synchronous serial communication.
Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB First/LSB First Selects the serial data is transmitted in MSB first or LSB first. 0: LSB first 1: MSB first 6 CPOS 0 R/W Clock Polarity Selection Selects SSCK clock polarity. 0: High output in idle mode, and low output in active mode 1: Low output in idle mode, and high output in active mode 5 CPHS 0 R/W Clock Phase Selection Selects SSCK clock phase. 0: Data changes at the first edge 1: Data is latched at the first edge 4, 3 2 1 0 CKS2 CKS1 CKS0 All 0 0 0 0 R/W R/W R/W Reserved The write value should always be 0. Transfer Clock Rate Selection Select the transfer clock rate (prescaler division rate) when a master mode is selected. 000: /2 001: /4 010: /8 011: /16 100: /32 101: /64 110: /128 111: /256
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Section 16 Synchronous Serial Communication Unit (SSU)
16.3.4
SS Enable Register (SSER)
SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable.
Bit 7 6 5, 4 3 Bit Name TE RE TEIE Initial Value 0 0 All 0 0 R/W R/W R/W R/W Description Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Reserved The write value should always be 0. Transmit End Interrupt Enable When this bit is set to 1, TEI interrupt request is enabled. 2 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. 1 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI interrupt request is enabled. 0 CEIE 0 R/W Conflict Error Interrupt Enable When this bit is set to 1, CEI interrupt request is enabled.
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Section 16 Synchronous Serial Communication Unit (SSU)
16.3.5
SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit 7 6 Bit Name ORER Initial Value 0 0 R/W R/W Description Reserved The write value should always be 0. Overrun Error If the next data is received while RDRF = 1, an overrun error occurs, indicating abnormal termination. SSRDR stores 1-frame receive data before an overrun error occurs and loses data received later. While ORER = 1, continuous serial reception cannot be continued. Serial transmission cannot be continued, either. [Setting condition] * When the next reception data is transferred to SSRDR while RDRF = 1 When 0 is written to ORER after reading ORER = 1
[Clearing condition] * 5, 4 3 TEND All 0 1 R
Reserved The write value should always be 0. Transmit End [Setting condition] * When the last bit of transmit data is transmitted with TDRE = 1 When 0 is written to the TEND bit after reading TEND = 1 When data is written to SSTDR
[Clearing conditions] * *
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Section 16 Synchronous Serial Communication Unit (SSU) Bit 2 Bit Name TDRE Initial Value 1 R/W R/W Description Transmit Data Register Empty Indicates whether or not SSTDR contains transmit data. [Setting conditions] * * When the TE bit in SSER is 0 When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to. When 0 is written to the TDRE bit after reading TDRE = 1 When data is written to SSTDR with TE = 1
[Clearing conditions] * * 1 RDRF 0 R/W
Receive Data Register Full Indicates whether or not SSRDR contains received data. [Setting condition] * When receive data is transferred from SSTRSR to SSRDR after successful data reception When 0 is written to RDRF after reading RDRF = 1 When received data is read from SSRDR
[Clearing conditions] * *
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Section 16 Synchronous Serial Communication Unit (SSU) Bit 0 Bit Name CE Initial Value 0 R/W R/W Description Conflict/Incomplete Error Indicates that a conflict error has occurred when 0 is externally input via the pin with MSS = 1. If the pin level changes to 1 during slave operation, an incomplete error occurs because it is determined that a master device has terminated the transfer. Data reception does not continue while the CE bit is set to 1. Reset the SSU internal sequencer by setting the SRES bit in SSCRL to 1 before resuming transfer after incomplete error. [Setting conditions] * * When a low level is input to the pin in master device mode (MSS in SSCRH = 1) When a 1 is input to the pin during slave device mode (MSS in SSCRH = 0) transfer When 0 is written to the CE bit after reading CE = 1
[Clearing condition] *
16.3.6
SS Transmit Data Register 3 to 0 (SSTDR3 to SSTDR0)
SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0 and SSTDR1 are valid. When 32-bit data length is selected, SSTDR3 to SSTDR0 are valid. Do not attempt to access invalid SS transmit data registers. When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to SSTRSR and starts transmission. If the next transmit data has already been written to SSTDR during serial transmission, the SSU transfers the written data to SSTRSR to continue transmission. Although SSTDR can be read or written to by the CPU and DTC at all times, to achieve reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is set to 1. The initial value of this register is H'00.
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SCS
SCS
SCS
SCS
Section 16 Synchronous Serial Communication Unit (SSU)
16.3.7
SS Receive Data Register 3 to 0 (SSRDR3 to SSRDR0)
SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0 and SSRDR1 are valid. When 32-bit data length is selected, SSRDR3 to SSRDR0 are valid. Do not attempt to access invalid SS receive data registers. When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to SSRDR where it is stored. After this, SSTRSR is receive-enabled. Since SSTRSR and SSRDR function as a double buffer in this way, continuous receive operations can be performed. Read SSRDR after confirming that the RDRF bit in SSSR is set to 1. SSRDR cannot be written to by the CPU. The initial value of this register is H'00. 16.3.8 SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data. When data from SSTDR to SSTRSR is transferred with MLS = 0, bit 0 of transmit data is bit 0 in the SSTDR contents (LSB first communication). When data from SSTDR to SSTRSR is transferred with MLS = 1, bit 0 of transmit data is bit 7 in the SSTDR contents (MSB first communication). To perform serial data transmission, the SSU transfers data starting from LSB (bit 0) in SSTRSR to the SSO pin. In reception, the SSU sets serial data that has been input from the SSI pin to SSTRSR starting from LSB (bit 0) and converts it into parallel data. When 1-byte data has been received, the SSTRSR contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed by the CPU.
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Section 16 Synchronous Serial Communication Unit (SSU)
16.4
16.4.1
Operation
Transfer Clock
A transfer clock can be selected from eight internal clocks and an external clock. When using this module, set SCKS in SSCRH to 1 to select the SSCK pin as a serial clock. When MSS in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin. 16.4.2 Relationship of Clock Phase, Polarity, and Data
The relationship of clock phase, polarity, and transfer data depends on the combination of CPOS and CPHS in SSMR. Figure 16.2 shows the relationship. Setting the MLS bit specifies that MSB or LSB first communication. When MLS = 0, data is transferred from the LSB to MSB. When MLS = 1, data is transferred from the MSB to LSB.
(1) When CPHS = 0 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO (2) When CPHS = 1 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Figure 16.2 Relationship of Clock Phase, Polarity, and Data
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Section 16 Synchronous Serial Communication Unit (SSU)
16.4.3
Relationship between Data I/O Pins and the Shift Register
The connection between data I/O pins and the shift register (SSTRSR) depends on the combination of the MSS and BIDE bits in SSCRH. Figure 16.3 shows the connection. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 16.3 (1)). The SSU transmits serial data from the SSI pin and receives serial data from the SSO pin when operating with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 16.3 (2)). The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode when operating with BIDE = 1 (bidirectional mode) (see figure 16.3 (3) and (4)). However, even if both the TE and RE bits are set to 1, transmission and reception are not performed simultaneously. Either the TE or RE bit must be selected.
(1) When BIDE = 0 (standard mode), MSS = 1, TE = 1, and RE = 1 SSCK (2) When BIDE = 0 (standard mode), MSS = 0, TE = 1, and RE = 1 SSCK
Shift register (SSTRSR)
SSO
Shift register (SSTRSR)
SSO
SSI
SSI
(3) When BIDE = 1 (bidirectional mode), MSS = 1, and TE or RE = 1 (4) When BIDE=1 (bidirectional mode), MSS = 0, and TE or RE = 1 SSCK SSCK
Shift register (SSTRSR)
SSO
Shift register (SSTRSR)
SSO
SSI
SSI
Figure 16.3 Relationship between Data I/O Pins and the Shift Register
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Section 16 Synchronous Serial Communication Unit (SSU)
16.4.4
Data Transmission and Data Reception
The SSU performs data communications using the bus with four lines: the clock line (SSCK), data input (SSI or SSO), data output (SSI or SSO), and chip select (SCS). The SSU also supports bidirectional mode in which the data is output and input using one pin. SSU Initialization Figure 16.4 shows an example of the SSU initialization. Before transmitting and receiving data, first clear the TE and RE bits in SSER to 0, then initialize the SSU. Note: When the operating mode or transfer format is changed for example, the TE and RE bits must be cleared to 0. When the TE bit is cleared to 0, the TDRE bit is set to 1. Note that clearing the RE bit to 0 does not initialize the values of the RDRF and ORER bits or the contents of SSRDR.
Start initialization
Clear TE and RE bits in SSER to 0
[1] Specify master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. [2] Specify transmit/receive data length.
[1]
Specify CSS1, CSS0, MSS, BIDE, SOL, and SCKS bits
[3] Specify MSB first/LSB first selection, clock polarity selection, clock phase selection, and transfer clock rate selection. [4] Specify enable/disable of interrupt request to the CPU.
[2]
Specify bits DATS1 and DATS0
[3]
Specify CKS2 to CKS0, MLS, CPOS, and CPHS bits
[4]
Specify TE, RE, TEIE, TIE, RIE, and CEIE bits simultaneously
End
Figure 16.4 Example of SSU Initialization
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Section 16 Synchronous Serial Communication Unit (SSU)
Data Transmission Figure 16.5 shows an example of transmission operation, and figure 16.6 shows an example of data transmission flowchart. When transmitting data, the SSU operates as shown below. In master device mode, the SSU outputs a transfer clock and data. In slave device mode, when a pin and a transfer clock is input to the SSCK pin, the SSU low level signal is input to the outputs data in synchronization with the transfer clock. Writing transmit data to SSTDR after initialization of the SSU automatically clears the TDRE bit in SSSR to 0, and the contents of SSTDR is transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been transferred with the TDRE bit cleared to 0, the SSTDR contents are transferred to SSTRSR to start the next transmission. When the 8th bit of transmit data has been transferred with the TDRE bit set to 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the SSCK pin is fixed at a high level when CPOS = 0 and at a low level when CPOS = 1. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0.
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SCS
Section 16 Synchronous Serial Communication Unit (SSU)
(1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0 1 frame SCS 1 frame
SSCK SSO
Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
SSTDR0 (LSB first transmission)
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0
SSTDR0 (MSB first transmission)
TDRE TEND LSI operation User operation
TXI interrupt generated TEI interrupt generated TXI interrupt generated TEI interrupt generated
Data written to Data written to SSTDR0 SSTDR0 (2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0 SCS 1 frame
SSCK SSO (LSB first) SSO (MSB first) TDRE TEND LSI operation User operation Data written to SSTDR1 to SSTDR0 TXI interrupt generated TEI interrupt generated
Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
SSTDR1
Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
SSTDR0
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0
SSTDR0
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0
SSTDR1
(3) When 32-bit data length is selected (SSTDR0, SSTDR1, SSTDR2, and SSTDR3 are valid) with CPOS = 0 and CPHS = 0 SCS 1 frame
SSCK SSO (LSB first) SSO (MSB first) TDRE TEND LSI operation User operation Data written to SSTDR3 to SSTDR0
TXI interrupt generated TEI interrupt generated Bit 0 to Bit Bit 0 7 to Bit Bit 7 0 to Bit 7 Bit 0 to Bit 7
SSTDR3
SSTDR2
SSTDR1
SSTDR0
Bit 7
to
Bit Bit 7 0
to
Bit 0
Bit 7
to
Bit Bit 0 7
to
Bit 0
SSTDR0
SSTDR1
SSTDR2
SSTDR3
Figure 16.5 Example of Transmission Operation
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Section 16 Synchronous Serial Communication Unit (SSU)
Start [1] [2] Initialization Read TDRE in SSR TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferd from SSTDR to SSTRSR Set TDRE to 1 to start transmission [3] Continuous data transmission? No Read TEND in SSSR TEND = 1? Yes Clear TEND to 0 Wait Confirm TEND = 0 [4] 1-bit interval elapsed ? Yes Clear TE in SSER to 0 End transmission Note: Hatching boxes represent SSU internal operations. No No Yes No
[1] Initialization: Specify the settings such as transmit data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Procedure for continuous data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Transmission end procedure: To end transmission, confirm TEND = 1 and wait until the last bit is surely transmitted, then set TE to 0.
Figure 16.6 Example of Data Transmission Flowchart
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Section 16 Synchronous Serial Communication Unit (SSU)
Data Reception Figure 16.7 shows an example of reception operation, and figure 16.8 shows an example of data reception flowchart. When receiving data, the SSU operates as shown below. After initialization, the SSU dummy-reads SSRDR and data reception is started. In master device mode, the SSU outputs a transfer clock and receives data. In slave device mode, pin and a transfer clock is input to the SSCK pin, the when a low level signal is input to the SSU receives data in synchronization with the transfer clock. When 1-frame data has been received, the received data is stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR.
SCS
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Section 16 Synchronous Serial Communication Unit (SSU)
(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0 SCS 1 frame 1 frame
SSCK SSI
Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
SSTDR0 (LSB first transmission)
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 10
SSTDR0 (MSB first transmission)
RDRF LSI operation User operation Dummy-read SSRDR0
RXI interrupt generated RXI interrupt generated
Read SSRDR0
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0 SCS 1 frame
SSCK SSI (LSB first) SSI (MSB first)
Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7
SSRDR1
Bit Bit Bit Bit Bit Bit Bit Bit 7 0 1 2 3 4 5 6
SSRDR0
Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0
SSRDR0
Bit Bit Bit Bit Bit Bit Bit Bit 0 7 6 5 4 3 2 1
SSRDR1
RDRF LSI operation User operation Dummy-read SSRDR0
RXI interrupt generated
(3) When 32-bit data length is selected (SSRDR0, SSRDR1, SSRDR2, and SSRDR3 are valid) with CPOS = 0 and CPHS = 0 SCS
SSCK SSI (LSB first) SSI (MSB first) RDRF LSI operation User operation Dummy-read SSRDR0
RXI interrupt generated Bit 0 to Bit Bit 7 0 to Bit Bit 7 0 to Bit 7 Bit 0 to Bit 7
SSRDR3
SSRDR2
SSRDR1
SSRDR0
Bit 7
to
Bit Bit 0 7
to
Bit 0
Bit 7
to
Bit Bit 0 7
to
Bit 0
SSRDR0
SSRDR1
SSRDR2
SSRDR3
Figure 16.7 Example of Reception Operation
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Section 16 Synchronous Serial Communication Unit (SSU)
Start [1] [2] Initialization Dummy-read SSRDR
[1] [2]
Initialization: Specify the settings such as receive data format. Start reception: When SSRDR is dummy-read with RE = 1, reception is started.
Read SSRDR No RDRF = 1? Yes ORER = 1? No [4] Continuous data reception? Yes Read received data in SSRDR RDRF automatically cleared No Yes [3]
[3], [6] Receive error processing: When a receive error occurs execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, reception is not resumed. [4] To continue single reception: When continuing single reception, the next single reception starts after reading received data in SSRDR. To complete reception: To complete reception, read received data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed.
[5]
[5]
RE = 0 Read received data in SSRDR End reception
[6]
Overrun error processing Clear ORER in SSSR End reception
Note: Hatching boxes represent SSU internal operations.
Figure 16.8 Example of Data Reception Flowchart
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Section 16 Synchronous Serial Communication Unit (SSU)
Data Transmission/Reception Figure 16.9 shows an example of simultaneous transmission/reception operation. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1. When the RDRF has been set to 1 at the 8th rising edge of the transfer clock (in a case of 8-bit data length), the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data transmission/reception is stopped. While the ORER bit in SSSR is set to 1, transmission/reception is not performed. To resume the transmission/reception, clear the ORER bit to 0. Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE and RE bits to 1.
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Section 16 Synchronous Serial Communication Unit (SSU)
[1] Initialization: Specify the settings such as transmit/receive data format. [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. [3] Check the SSU state: Read SSSR and confirm that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. [5] Procedure for continuous data transmission/ reception: To continue serial data transmission/reception, confirm that the TDRE bit 1meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR.
Start [1] [2] Initialization Read TDRE in SSSR TDRE = 1? Yes Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR [3] No RDRF = 1? Yes ORER = 1? No Read received data in SSRDR RDRF automatically cleared Continuous data transmission/reception No Read TEND in SSSR TEND = 1? Yes Clear TEND in SSSR to 0 No Error processing No [5] Yes Yes [4] No
1-bit internal elapsed? Yes Clear TE and RE in SSER to 0
End transmission/reception Note: Hatching boxes represent SSU internal operations.
Figure 16.9 Example of Simultaneous Transmission/Reception Flowchart
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Section 16 Synchronous Serial Communication Unit (SSU)
When bits CSS1 and CSS0 in SSCRH are specified to B'10, the pin functions as an input (Hi-Z) to detect conflict error. The conflict detection period starts when setting the MSS bit in SSCRH to 1 and ends when starting serial transfer. When a low level signal is input to the pin within the period, a conflict error occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0. Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0 before resuming the transmission or reception.
External input to SCS
Internal-clocked SCS
MSS
Transfer enabled internal signal CE Data written to SSTDR (Hi-Z)
SCS output
Conflict error detection period
Worst time for internally clocking SCS
Figure 16.10 Conflict Error Detection Timing (Before Transfer Start)
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SCS
SCS
SCS
16.4.5
Pin Control and Conflict Error
Section 16 Synchronous Serial Communication Unit (SSU)
SCS
(Hi-Z)
MSS
Transfer enabled internal signal CE Transfer end Conflict error detection period
Figure 16.11 Conflict Error Detection Timing (After Transfer End)
16.5
Interrupt Requests
The SSU interrupt requests consist of transmit data register empty, transmit end, receive data register full, overrun error, and conflict error. Of these interrupt sources, transmit data register empty, transmit end, receive data register full can activate the DTC for data transfer. The TDRE, TEND, and RDRF bits are automatically cleared to 0 by the DTC data transfer. Since these interrupt requests are allocated to four vector addresses: SSEr_i0, SSRx_i0, SSTx_i0 and SSERT_i1, the interrupt sources must be distinguished by flags. Table 16.2 lists interrupt sources.
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Section 16 Synchronous Serial Communication Unit (SSU)
Table 16.2 Interrupt Souses
Channel 0 Abbreviation SSEr_i0 Interrupt Request Overrun error Conflict error SSRx_i0 SSTx_i0 Receive data register full Transmit data register empty Transmit end 1 SSERT_i1 Overrun error Conflict error Receive data register full Transmit data register empty Transmit end Symbol OEI CEI RXI TXI TEI OEI CEI RXI TXI TEI Interrupt Condition RIE = 1, ORER = 1 CEIE = 1, CE = 1 RIE = 1, RDRF = 1 TIE = 1, TDRE = 1 TEIE = 1, TEND = 1 RIE = 1, ORER = 1 CEIE = 1, CE = 1 RIE = 1, RDRF = 1 TIE = 1, TDRE = 1 TEIE = 1, TEND = 1
When interrupt conditions shown in table 16.2 are satisfied and the I bit in CCR is 0, the CPU executes interrupt exception processing. Clear each interrupt source in the exception processing.
16.6
16.6.1
Usage Note
Setting of Module Stop Mode
The SSU can be enabled/disabled by the module stop control register setting and is disabled by the initial value. Canceling module stop mode enables to access the SSU registers. For details, see section 21, Power-Down Modes.
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Section 17 A/D Converter
Section 17 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. The block diagram of the A/D converter is shown in figure 17.1.
17.1
* * * *
Features
* * *
* *
10-bit resolution Sixteen input channels Conversion time: 11.08 s per channel (at 24 MHz operation) Two operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels Four data registers Conversion results are held in a 16-bit data register for each channel Sample and hold function Three conversion start methods Software 16-bit timer pulse unit (TPU) conversion start trigger External trigger signal Interrupt request An A/D conversion end interrupt request (ADI) can be generated Module stop mode can be set
ADCMS38A_000020020300
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Section 17 A/D Converter
Module data bus
Bus interface
Internal data bus
AVCC Vref AVSS 10-bit D/A
Successive approximations register
A D D R A
A D D R B
A D D R C
A D D R D
A D C S R
A D C R
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ADTRG
+
/2 /4
Comparator
Multiplexer
Control circuit
/8 /16
Sample-andhold circuit
ADI interrupt Conversion start trigger from TPU
Legend: ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A
ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D
Figure 17.1 Block Diagram of A/D Converter
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Section 17 A/D Converter
17.2
Input/Output Pins
Table 17.1 summarizes the input pins used by the A/D converter. 12 analog input pins are divided into three groups, each of which includes four channels; analog input pins 3 to 0 (AN3 to AN0) comprising group 0, analog input pins 7 to 4 (AN7 to AN4) comprising group 1, analog input pins 11 to 8 (AN11 to AN8) comprising group 2, and analog input pins 15 to 12 (AN15 to AN12) comprising group 3. The AVcc and AVss pins are the power supply pins for the A/D converter analog section. The Vref pin is the A/D conversion reference voltage pin. Table 17.1 Pin Configuration
Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 A/D external trigger input pin Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input pin for starting A/D conversion Group 3 analog input pins Group 2 analog input pins Group 1 analog input pins Function Analog section power supply and reference voltage Analog section ground and reference voltage Reference voltage of A/D conversion Group 0 analog input pins
GRTDA
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Section 17 A/D Converter
17.3
Register Description
The A/D converter has the following registers. Module stop mode for the A/D converter is specified with the MSTPA1 bit in the module stop control register (MSTPCRA). For details on the module stop control register A (MSTPCRA), refer to section 21.1.2, Module Stop Control Register A to C (MSTPCRA to MSTPCRC). * A/D data register A (ADDRA) * A/D data register B (ADDRB) * A/D data register C (ADDRC) * A/D data register D (ADDRD) * A/D control/status register (ADCSR) * A/D control register (ADCR) 17.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers to store conversion results for each channel are shown in table 17.2. The converted 10-bit data is stored in bits 6 to 15 in ADDR. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading the ADDR, always read the upper byte first, and then read the lower byte, or read in word unit. Otherwise, the read contents are not guaranteed. Table 17.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel CH3 = 0 Group 0 (CH2 = 0) AN0 AN1 AN2 AN3 Group 1 (CH2 = 1) AN4 AN5 AN6 AN7 Group 2 (CH2 = 0) AN8 AN9 AN10 AN11 CH3 = 1 Group 3 (CH2 = 1) AN12 AN13 AN14 AN15 A/D Data Register to Store the A/D Conversion Results ADDRA ADDRB ADDRC ADDRD
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Section 17 A/D Converter
17.3.2
A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit 7 Bit Name ADF Initial Value 0 R/W R/(W) Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all specified channels selected in scan mode
[Clearing conditions] * * When 0 is written after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read
6
ADIE
0
R/W
A/D Interrupt Enable A/D conversion end interrupt (ADI) is enabled when this bit is set to 1.
5
ADST
0
R/W
A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters the wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bits is automatically cleared to 0 when conversion on the specified channel is complete. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to software standby mode, hardware standby mode or module stop mode.
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Section 17 A/D Converter Bit 4 Bit Name SCAN Initial Value 0 R/W R/W Description Scan Mode Selects the A/D conversion operating mode. 0: Single mode 1: Scan mode 3 2 1 0 CH3 CH2 CH1 CH0 0 0 0 0 R/W R/W R/W R/W Channel Select 0 to 3 Select analog input channels. When SCAN = 0 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1000: AN8 1001: AN9 1010: AN10 1011: AN11 1100: AN12 1101: AN13 1110: AN14 1111: AN15 When SCAN = 1 0000: AN0 0001: AN1, AN0 0010: AN2 to AN0 0011: AN3 to AN0 0100: AN4 0101: AN5, AN4 0110: AN6 to AN4 0111: AN7 to AN4 1000: AN8 1001: AN9, AN8 1010: AN10 to AN8 1011: AN11 to AN8 1100: AN12 1101: AN13, AN12 1110: AN14 to AN12 1111: AN15 to AN12
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Section 17 A/D Converter
17.3.3
A/D Control Register (ADCR)
The ADCR enables A/D conversion started by an external trigger signal.
Bit 7 6 Bit Name TRGS1 TRGS0 Initial Value 0 0 R/W R/W R/W Description Timer Trigger Select 1 and 0 Enable the start of A/D conversion by a trigger signal. Bits TRGS0 and TRGS1 should be set while A/D conversion is stopped (ADST = 0). 00: A/D conversion is started by software 01: A/D conversion is started by TPU conversion start trigger 10: Start of A/D conversion by 8-bit timer conversion start trigger is allowed 5, 4 3 2 CKS1 CKS0 All 1 0 0 R/W R/W Reserved These bits are always read as 1. Clock Select 1 and 0 Specify the A/D conversion time. The conversion time should be changed only when ADST = 0. Specify a value within the range shown in table 23.7. 00: Conversion time = 530 states (max.) 01: Conversion time = 266 states (max.) 10: Conversion time = 134 states (max.) 11: Conversion time = 68 states (max.) 1, 0 All 1 Reserved These bits are always read as 1.
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GRTDA
11: A/D conversion is started by the
pin
Section 17 A/D Converter
17.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, clear the ADST bit in ADCSR to 0 first in order to prevent incorrect operation. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 17.4.1 Single Mode
In single mode, A/D conversion is performed only once on the specified single channel as follows. 1. A/D conversion is started when the ADST bit is set to 1 by software or external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit retains 1 during A/D conversion. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the wait state. If the ADST bit is cleared to 0 during A/D conversion, the conversion is stopped and the A/D converter enters the wait state. 17.4.2 Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the specified channels up to four channels as follows. 1. When the ADST bit is set to 1 by software, TPU or external trigger input, A/D conversion starts on the first channel in the group (for example, AN0 when CH3 and CH2 = 00, AN4 when CH3 and CH2 = 01, AN8 when CH3 and CH2 = 10, or AN12 when CH3 and CH2 = 11). 2. When the A/D conversion is completed on one channel, the result is sequentially transferred to the A/D data register corresponding to the channel. 3. When the conversion is completed on all the selected channels, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Then, the A/D converter restarts the conversion from the first channel in the group. 4. Steps 2 to 3 are repeated as long as the ADST bit is set to 1. When the ADST bit is cleared to 0, the A/D conversion stops and the A/D converter enters the wait state.
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Section 17 A/D Converter
17.4.3
Input Sampling and A/D Conversion Time
The A/D converter includes the sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, and then conversion is started. Figure 17.2 shows the A/D conversion timing. Table 17.3 shows the A/D conversion time. As shown in figure 17.2, the A/D conversion time (tCONV) includes tD and input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. Therefore, the total conversion time varies within the range shown in table 17.3. In scan mode, the values given in table 17.3 indicate the first conversion time. The second and subsequent conversion time is shown in table 17.4. In both cases, set bits CKS1 and CKS0 in ADCR within the range shown in table 23.7.
(1) Address (2)
Write signal Input sampling timing
ADF tD tSPL tCONV Legend: (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time
Figure 17.2 A/D Conversion Timing
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Section 17 A/D Converter
Table 17.3 A/D Conversion Time (Single Mode)
CKS1 = 0 CKS0 = 0 Item Symbol Min Typ Max 18 33 CKS0 = 1 Min Typ Max 10 63 17 266 CKS1 = 1 CKS0 = 0 Min Typ Max 6 31 9 134 CKS0 = 1 Min Typ Max 4 67 15 5 68
A/D conversion tD start delay Input sampling time tSPL
127 530
A/D conversion tCONV time
515
259
131
Note: All values represent the number of states.
Table 17.4 A/D Conversion Time (Scan Mode)
CKS1 0 1 CKS0 0 1 0 1 Conversion Time (State) 512 (Fixed) 256 (Fixed) 128 (Fixed) 64 (Fixed)
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Section 17 A/D Converter
17.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When bits TRGS0 and TRGS1 in ADCR are set to 11, an external trigger is input on the pin. At the falling edge of the pin, the ADST bit in ADCSR is set to 1, and the A/D conversion starts. Other operations are the same as when the ADST bit has been set to 1 by software in both single and scan modes. Figure 17.3 shows the timing.
ADTRG
Internal trigger signal
ADST A/D conversion
Figure 17.3 External Trigger Input Timing
17.5
Interrupt Source
When A/D conversion is completed, the A/D converter generates an A/D conversion end interrupt (ADI). The ADI interrupt request is enabled when the ADIE bit is set to 1 while the ADF bit in ADCSR is set to 1 after A/D conversion is completed. The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion without imposing a load on software. Table 17.5 A/D Converter Interrupt Source
Name ADI Interrupt Source A/D conversion completed Interrupt Source Flag ADF DTC Activation Possible
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GRTDA
GRTDA
Section 17 A/D Converter
17.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 17.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 17.5). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between zero voltage and fullscale voltage. Does not include offset error, full-scale error, or quantization error (see figure 17.5). * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
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Section 17 A/D Converter
Digital output
111 110 101 100 011 010 001 000
Ideal A/D conversion characteristic
Quantization error
1 2 1024 1024
1022 1023 FS 1024 1024 Analog input voltage
Figure 17.4 A/D Conversion Accuracy Definitions
Full-scale error
Digital output
Ideal A/D conversion characteristic
Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage
Offset error
Figure 17.5 A/D Conversion Accuracy Definitions
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Section 17 A/D Converter
17.7
17.7.1
Usage Notes
Module Stop Mode Setting
Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes. 17.7.2 Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 17.6). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 17.7.3 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e., acting as antennas).
This LSI Sensor output impedance to 5 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF
A/D converter equivalent circuit 10 k 20 pF
Figure 17.6 Example of Analog Input Circuit
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Section 17 A/D Converter
17.7.4
Range of Analog Power Supply and Other Pin Settings
If the conditions below are not met, the reliability of the device may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VNn AVcc. * Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss as the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. * Setting range of the Vref pin The reference voltage set by the Vref pin should be in the range Vref AVcc. 17.7.5 Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN15 to AN0) and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss) on the board. 17.7.6 Notes on Noise Countermeasures
A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN15 to AN0), between AVcc and AVss, as shown in figure 17.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN15 to AN0 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN15 to AN0) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding circuit constants.
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Section 17 A/D Converter
AVCC Rin*2 *1 0.1 F 100 AN0 to AN15 AVSS
Notes: Values are reference values. 1. 10 F 0.01 F
2. Rin: Input impedance
Figure 17.7 Example of Analog Input Protection Circuit Table 17.6 Analog Pin Specifications
Item Analog input capacitance Permissible signal source impedance Min Max 20 5 Unit pF k
10 k AN15 to AN0 To A/D converter 20 pF
Note: Values are reference values.
Figure 17.8 Analog Input Pin Equivalent Circuit
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Section 18 RAM
Section 18 RAM
The H8S/2628 has 8 kbytes, and the H8S/2627 has 6 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR).
Product Model H8S/2628 Group HD64F2628 HD6432628 HD6432627 ROM Type Flash memory version Masked ROM version Capacity 8 kbytes 8 kbytes 6 kbytes Address H'FFD000 to H'FFEFBF H'FFD000 to H'FFEFBF H'FFD800 to H'FFEFBF
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Section 18 RAM
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Section 19 ROM
Section 19 ROM
The features of the flash memory are summarized below. The block diagram of the flash memory is shown in figure 19.1.
19.1
Features
* Size: 128 kbytes * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 32 kbytes x 2 blocks, 28 kbytes x 1 block, 16 kbytes x 1 block, 8 kbytes x 2 blocks, and 1 kbyte x 4 blocks. To erase the entire flash memory, each block must be erased in turn. * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * Three programming modes Boot mode User mode Programmer mode On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasing.
ROM3120B_000020020900
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Section 19 ROM
Internal address bus
Internal data bus (16 bits)
Module bus
FLMCR1 FLMCR2 EBR1 EBR2 RAMER Bus interface/controller Operating mode FWE pin Mode pins
Flash memory (128 kbytes)
Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER:
Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register
Figure 19.1 Block Diagram of Flash Memory
19.2
Mode Transitions
When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 19.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 19.1. Figure 19.3 shows the operation flow for boot mode and figure 19.4 shows that for user program mode.
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Section 19 ROM
MD1 = 1, MD2 = 1, FWE = 0
Reset state
*1 User mode (on-chip ROM enabled)
RES = 0
RES = 0
MD1 = 1, MD2 = 1, FWE = 1 RES = 0 MD2 = 0, MD1 = 1, FWE = 1 RES = 0
*2
FWE = 1
FWE = 0
Programmer mode
User program mode
*1
Boot mode On-board programming mode
Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. This LSI transits to programmer mode by using the dedicated PROM programmer.
Figure 19.2 Flash Memory State Transitions Table 19.1 Differences between Boot Mode and User Program Mode
Boot Mode Total erase Block erase Programming control program* Yes No (2) User Program Mode Yes Yes (1) (2) (3)
(1) Erase/erase-verify (2) Program/program-verify (3) Emulation Note: * To be provided by the user, in accordance with the recommended algorithm.
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Section 19 ROM
1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host.
2. Programming control program transfer When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area.
Host
Host Programming control program New application program
New application program
This LSI
Boot program Flash memory RAM SCI
This LSI
Boot program Flash memory RAM Boot program area SCI
Application program (old version)
Application program (old version)
Programming control program
3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks.
Host
4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory.
Host
New application program
This LSI
Boot program Flash memory RAM Boot program area Flash memory preprogramming erase
Programming control program
This LSI
SCI Boot program Flash memory RAM Boot program area New application program
Programming control program
SCI
Program execution state
Figure 19.3 Boot Mode
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Section 19 ROM
1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory.
Host Programming/ erase control program New application program
2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM.
Host
New application program
This LSI
Boot program Flash memory
FWE assessment program
This LSI
SCI RAM Boot program Flash memory
FWE assessment program
SCI RAM
Transfer program
Transfer program
Programming/ erase control program
Application program (old version)
Application program (old version)
3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units.
Host
4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks.
Host
New application program
This LSI
Boot program Flash memory
FWE assessment program
This LSI
SCI RAM Boot program Flash memory
FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program
SCI RAM
Transfer program
Flash memory erase
New application program
Program execution state
Figure 19.4 User Program Mode
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Section 19 ROM
19.3
Block Configuration
Figure 19.5 shows the block configuration of 128-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 32 kbytes (2 blocks), 28 kbytes (1 block), 16 kbytes (1 block), 8 kbytes (2 blocks), and 1 kbyte (4 blocks). Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
EB0 Erase unit 1 kbyte EB1 Erase unit 1 kbyte EB2 Erase unit 1 kbyte EB3 Erase unit 1 kbyte EB4 Erase unit 28 kbytes EB5 Erase unit 16 kbytes EB6 Erase unit 8 kbytes EB7 Erase unit 8 kbytes EB8 Erase unit 32 kbytes EB9 Erase unit 32 kbytes
H'000000 H'000380 H'000400
H'000001 H'000381 H'000401
H'000002 H'000382 H'000402
Programming unit: 128 bytes
H'00007F H'0003FF
Programming unit: 128 bytes
H'00047F H'0007FF
H'000780 H'000800 H'000B80 H'000C00
H'000781 H'000801 H'000B81 H'000C01
H'000782 H'000802 H'000B82 H'000C02 Programming unit: 128 bytes Programming unit: 128 bytes
H'00087F
H'000BFF H'000C7F H'000FFF Programming unit: 128 bytes H'00107F H'007FFF Programming unit: 128 bytes H'00807F H'00BFFF Programming unit: 128 bytes H'00C07F H'00DFFF Programming unit: 128 bytes H'00E07F
H'000F80 H'001000 H'007F80 H'008000 H'00BF80 H'00C000
H'000F81 H'001001 H'007F81 H'008001 H'00BF81 H'00C001
H'000F82 H'001002 H'007F82 H'008002 H'00BF82 H'00C002
H'00DF80 H'00E000 H'00FF80 H'010000
H'00DF81 H'00E001 H'00FF81 H'010001
H'00DF82 H'00E002 H'00FF82 H'010002 Programming unit: 128 bytes
H'00FFFF H'01007F H'017FFF Programming unit: 128 bytes H'01807F
H'017F80 H'018000 H'01FF80
H'017F81 H'018001 H'01FF81
H'017F82 H'018002 H'01FF82
H'01FFFF
Figure 19.5 Flash Memory Block Configuration
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Section 19 ROM
19.4
Input/Output Pins
The flash memory is controlled by means of the pins shown in table 19.2. Table 19.2 Pin Configuration
Pin Name I/O Input Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets this LSI's operating mode Sets this LSI's operating mode Sets this LSI's operating mode Serial transmit data output Serial receive data input
19.5
The flash memory has the following registers. Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Erase block register 2 (EBR2) RAM emulation register (RAMER) 19.5.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 makes the flash memory enter program mode, program-verify mode, erase mode, or erase-verify mode. For details on the register setting, refer to section 19.8, Flash Memory Programming/ Erasing.
SER
FWE MD2 MD1 MD0 TxD2 RxD2
Register Descriptions
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Section 19 ROM Bit 7 Bit Name FWE Initial Value -- R/W R Description Reflects the input level at the FWE pin. It is set to 1 when a low level is input to the FWE pin, and cleared to 0 when a high level is input. Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 and EBR2 bits cannot be set. 5 ESU1 0 R/W Erase Setup When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. 4 PSU1 0 R/W Program Setup When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P1 bit in FLMCR1. 3 EV1 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV1 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, program-verify mode is cancelled. 1 E1 0 R/W Erase When this bit is set to 1 while the SWE1 and ESU1 bits are 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P1 0 R/W Program When this bit is set to 1 while the SWE1 and PSU1 bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled.
6
SWE
0
R/W
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Section 19 ROM
19.5.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 indicates the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Bit 7 Bit Name FLER Initial Value 0 R/W R Description Indicates that an error has occurred during flash memory programming or erasing. When the flash memory enters the error-protection state, this bit is set to 1. See section 19.9.3, Error Protection, for details. 6 to 0 -- All 0 -- Reserved These bits are always read as 0.
19.5.3
Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, otherwise, all the bits in EBR1 are automatically cleared to 0.
Bit 7 6 5 4 3 2 1 0 Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 8 kbytes of EB7 (H'00E000 to H'00FFFF) will be erased. When this bit is set to 1, 8 kbytes of EB6 (H'00C000 to H'00DFFF) will be erased. When this bit is set to 1, 16 kbytes of EB5 (H'008000 to H'00BFFF) will be erased. When this bit is set to 1, 28 kbytes of EB4 (H'001000 to H'007FFF) will be erased. When this bit is set to 1, 1 kbyte of EB3 (H'000C00 to H'000FFF) will be erased. When this bit is set to 1, 1 kbyte of EB2 (H'000800 to H'000BFF) will be erased. When this bit is set to 1, 1 kbyte of EB1 (H'000400 to H'0007FF) will be erased. When this bit is set to 1, 1 kbyte of EB0 (H'000000 to H'0003FF) will be erased.
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Section 19 ROM
19.5.4
Erase Block Register 2 (EBR2)
EBR2 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, otherwise, all the bits in EBR1 are be automatically cleared to 0.
Bit 7 to 2 1 0 Bit Name -- EB9 EB8 Initial Value All 0 0 0 R/W -- R/W R/W Description Reserved These bits are always read as 0. When this bit is set to 1, 32 kbytes of EB9 (H'018000 to H'01FFFF) will be erased. When this bit is set to 1, 32 kbytes of EB8 (H'010000 to H'017FFF) will be erased.
19.5.5
RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER settings should be made in user mode or user program mode. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. If accessed, normal access execution is not guaranteed.
Bit 7 6 5 4 3 Bit Name -- -- -- -- RAMS Initial Value 0 0 0 0 0 R/W R/W -- -- R/W Description Reserved These bits are always read as 0. Reserved Only 0 should be written to these bits. RAM Select Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, the flash memory is overlapped with part of RAM, and all flash memory blocks are program/eraseprotected.
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Section 19 ROM Bit 2 1 0 Bit Name RAM2 RAM1 RAM0 Initial Value 0 0 0 R/W R/W R/W R/W Description Flash Memory Area Selection Specifies one of the following flash memory areas to overlap the RAM area of H'FFE000 to H'FFE3FF when the RAMS bit is set to 1. The areas correspond with 1-kbyte erase blocks. 00x: H'000000 to H'0003FF (EB0) 01x: H'000400 to H'0007FF (EB1) 10x: H'000800 to H'000BFF (EB2) 11x: H'000C00 to H'000FFF (EB3) Legend: x: Don't care
19.6
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode enabling on-board programming/erasing and programmer mode enabling programming/erasing with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the MD pin settings and FWE pin setting, as shown in table 19.3. The input level of each pin must be defined four states before the reset ends. When boot mode is entered, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI_2. After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return in case that programming/erasing cannot be performed in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 19.3 Setting On-Board Programming Modes
MD2 1 0 MD1 1 1 MD0 1 1 FWE 1 1 LSI State after Reset End User Mode Boot Mode
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Section 19 ROM
19.6.1
Boot Mode
Table 19.4 shows the boot mode operations from a reset end to a branch to the programming control program. 1. In boot mode, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 19.8, Flash Memory Programming/Erasing. 2. SCI_2 should be set to asynchronous mode with the transfer format of 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI_2 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. When the bit rate matching is completed, the chip transmits 1-byte data H'00 to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit 1-byte data H'55 to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 19.5. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFE800 to H'FFEFBF is used to store the programming control program to be transferred from the host. The boot program area cannot be used until the execution is shifted to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI_2 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value is retained in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. At this time, the TxD pin is in the high level output state. The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. End the reset by driving the reset pin low, waiting at least 20 states, and then setting the mode (MD) pins. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the MD pin input level in boot mode.
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Section 19 ROM
9. All interrupts are disabled during programming or erasing of the flash memory. Table 19.4 Boot Mode Operation
Host Operation Processing Contents LSI Operation Processing Contents Branches to boot program at reset-start Boot program initiation Bit rate adjustment Continuously transmits data H'00 at specified bit rate H'00, H'00 ...... H'00
Item Boot mode start
Communications Contents
Transmits data H'55 when data H'00 is received error-free
H'00 H'55 H'AA
* Measures low-level period of receive data H'00 * Calculates bit rate and sets it in BRR of SCI_2 * Transmits data H'00 to host as adjustment end indication Transmits data H'AA to host when data H'55 is received
Receives data H'AA Transfer of programming control program Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) Transmits 1-byte of programming control program (repeated for N times) Flash memory erase Boot program erase error Receives data H'AA H'FF High-order byte and low-order byte Echobacks the 2-byte data received Echoback H'XX Echoback Echobacks received data to host and also transfers it to RAM (repeated for N times)
H'AA
Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host (If erase could not be done, transmits data H'FF to host and aborts operation) Branches to programming control program transferred to on-chip RAM and starts execution
Table 19.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible
Host Bit Rate 19,200 bps 9,600 bps 4,800 bps System Clock Frequency Range of LSI 24 MHz 24 to 8 MHz 24 to 4 MHz
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Section 19 ROM
19.6.2
Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. Since the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 19.6 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 19.8, Flash Memory Programming/Erasing.
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Section 19 ROM
Reset-start
No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program
Branch to user program/erase control program in RAM
FWE = high*
Execute user program/erase control program (flash memory rewrite)
Clear FWE
Branch to flash memory application program Note: * Do not constantly apply a high level to the FWE pin. Only apply a high level to the FWE pin when programming or erasing the flash memory. To prevent excessive programming or erasing, while a high level is being applied to the FWE pin, activate the watchdog timer in case of handling CPU runaways.
Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode
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Section 19 ROM
19.7
Flash Memory Emulation in RAM
A setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. Emulation can be performed in user mode or user program mode. Figure 19.7 shows an example of emulation of real-time flash memory programming. 1. Set RAMER to overlap part of RAM onto the area for which real-time programming is required. 2. Emulation is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing the RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0).
Start of emulation program
Set RAMER
Write tuning data to overlap RAM
Execute application program No
Tuning OK? Yes Clear RAMER
Write to flash memory emulation block
End of emulation program
Figure 19.7 Flowchart for Flash Memory Emulation in RAM
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Section 19 ROM
An example in which flash memory block area EB0 is overlapped is shown in figure 19.8. 1. The RAM area to be overlapped is fixed at a 1-kbyte area in the range H'FFE000 to H'FFE3FF. 2. The flash memory area to overlap is selected by RAMER from a 1-kbyte area of the EB0 to EB3 blocks. 3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. 4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). In this state, setting the P1 or E1 bit in FLMCR1 to 1 does not make a transition to program mode or erase mode. 5. A RAM area cannot be erased by execution of software in accordance with the erase algorithm. 6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM.
H'000000 Flash memory (EB0) H'0003FF H'000400 (EB1) H'0007FF H'000800 (EB2) H'000BFF H'000C00 (EB3) H'000FFF (EB3) Flash memory (EB2) On-chip RAM (Shadow of H'FFE000 to H'FFE3FF) Flash memory (EB0)
H'FFE000
On-chip RAM (1 kbyte)
On-chip RAM (1 kbyte)
H'FFE3FF Normal memory map Memory map with overlapped RAM
Figure 19.8 Example of RAM Overlap Operation
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Section 19 ROM
19.8
Flash Memory Programming/Erasing
The flash memory is programmed or erased in on-board programming mode by a software method using the CPU. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode perform programming/erasing in combination with these modes. Flash memory programming and erasing should be performed in accordance with the descriptions in section 19.8.1, Program/Program-Verify, and section 19.8.2, Erase/Erase-Verify, respectively. 19.8.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 19.9 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done on erased addresses. Do not perform additional programming or previously programmed addresses. 2. Programming should be performed in units of 128 bytes. A 128-byte data must be transferred even if data to be written is fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation and additional programming data computation according to figure 19.9. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P1 bit is set to 1 is the programming time. Figure 19.9 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. Set the overflow cycle to approximately 6.6 ms. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 8. The number of repetitions of the program/program-verify sequence for the same bit should be less than 1,000.
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Section 19 ROM
Write pulse application subroutine
Start of programming START Set SWE bit in FLMCR1 Wait (tsswe) s
Store 128-byte program data in program data area and reprogram data area
Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait (tspsu) s Set P bit in FLMCR1 Wait (tsp) s Clear P bit in FLMCR1 Wait (tcp) s Clear PSU bit in FLMCR1 Wait (tcpsu) s
Disable WDT
Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
*7 *4
*7
Start of programming
n=1 m=0
*5*7
End of programming
Write 128-byte data in RAM reprogram data area consecutively to flash memory
*1
Sub-Routine-Call
*7
Apply Write pulse Set PV bit in FLMCR1 Wait (tspv) s
H'FF dummy write to verify address
See Note 6 for pulse width
*7
*7
Wait (tspvr) s
Read verify data Increment address
*7 *2
No m=1 No
nn+1
End Sub
Note 6: Write Pulse Width Number of Writes n Write Time (tsp) s
Write data = verify data?
1 2 3 4 5 6 7 8 9 10 11 12 13
30 * 30 * 30 * 30 * 30 * 30 * 200 200 200 200 200 200 200
Yes 6n?
Yes Additional-programming data computation Transfer additional-programming data to additional-programming data area
Reprogram data computation
*4 *3 *4
Transfer reprogram data to reprogram data area 128-byte data verification completed?
998 999 1000
200 200 200
No
Yes Clear PV bit in FLMCR1 Reprogram Wait (tcpv) s 6 n? No
Note: * Use a 10 s write pulse for additional programming.
*7
RAM
Program data storage area (128 bytes)
Yes Successively write 128-byte data from additional*1 programming data area in RAM to flash memory Sub-Routine-Call Apply Write Pulse (Additional programming) No
Reprogram data storage area (128 bytes) Additional-programming data storage area (128 bytes)
*7
n (N) ?
m=0? Yes Clear SWE bit in FLMCR1
No
Yes Clear SWE bit in FLMCR1
Wait (tcswe) s Wait (tcswe) s *7 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, End of programming Programming failure H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. 5. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 7. The wait times and value of N are shown in 23.5, Flash Memory Characteristics. Reprogram Data Computation Table
Original Data Verify Data Reprogram Data
Additional-Programming Data Computation Table (X) 1 0 1 1
Still in erased state; no action Comments Programming completed Programming incomplete; reprogram
(D) 0 0 1 1
(V) 0 1 0 1
Reprogram Data (X') 0 0 1 1
Verify Data Additional(V) Programming Data (Y) 0 1 0 1 0 1 1 1
Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed
Figure 19.9 Program/Program-Verify Flowchart
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Section 19 ROM
19.8.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.10 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Specify a single block o be erased with the erase block registers (EBR2 and EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set the overflow cycle to approximately 19.8 ms. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. Note that the number of repetitions of the erase/erase-verify sequence should be less than 100. 19.8.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the interrupt, should be disabled while flash memory is being programmed, erased, or the boot program is being executed, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
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IMN
Section 19 ROM
Erase start SWE bit 1 Wait 1 s n1 Set EBR1 and EBR2 Enable WDT ESU1 bit 1 Wait 100 s E1 bit 1 Wait 10 ms E1 bit 0 Wait 10 s ESU1 bit 0 Wait 10 s Disable WDT EV1 bit 1 Wait 20 s
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 s Read verify data No
nn+1
Increment address
Verify data = all 1s? Yes No Last address of block? Yes EV1 bit 0 Wait 4 s No
EV1 bit 0 Wait 4 s Yes
All erase block erased? Yes SWE bit 0 Wait 100 s End of erasing
n 100? No SWE bit 0 Wait 100 s Erase failure
Figure 19.10 Erase/Erase-Verify Flowchart
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Section 19 ROM
19.9
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 19.9.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are pin, the reset state is not entered unless the pin is held low initialized. In a reset via the until oscillation settles after powering on. In the case of a reset during operation, hold the pin pulse width specified in the AC characteristics section. low for the 19.9.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P1 or E1 bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00, erase protection is set for all blocks. 19.9.3 Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling (excluding a reset) during programming/erasing * When a SLEEP instruction is executed during programming/erasing The FLMCR2, FLMCR1, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-
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SER
SER
SER
SER
Section 19 ROM
entered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset.
19.10
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the Renesas 128-kbyte flash memory on-chip MCU device type (FZTAT128V5A).
19.11
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read and written to. * Standby mode All flash memory circuits are halted. Table 19.6 shows the correspondence between the operating modes of the H8S/2628 Group and the flash memory. When the flash memory returns to its normal operating state from standby mode, a period to settle the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 s, even when the external clock is being used. Table 19.6 Flash Memory Operating States
LSI Operating State Active mode Standby mode Flash Memory Operating State Normal operating mode Standby mode
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Section 19 ROM
19.12
Note on Switching from F-ZTAT Version to Masked ROM Version
The masked ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 19.7 lists the registers that are present in the F-ZTAT version but not in the masked ROM version. If a register listed in table 19.7 is read in the masked ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a masked ROM version product, it must be modified to ensure that the registers in table 19.7 have no effect. Table 19.7 Registers Present in F-ZTAT Version but Absent in Masked ROM Version
Register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 RAMER Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB
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Section 20 Clock Pulse Generator
Section 20 Clock Pulse Generator
This LSI has an on-chip clock pulse generator that generates the system clock (), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL circuit, clock selection circuit, medium-speed clock divider, and bus master clock selection circuit. A block diagram of the clock pulse generator is shown in figure 20.1.
LPWRCR STC1, STC0 EXTAL Clock oscillator XTAL PLL circuit (x1, x2, x4) Clock selection circuit
SCKCR SCK2 to SCK0
Mediumspeed clock divider
/32 to /2
Bus master clock selection circuit
System clock to pin Legend: LPWRCR: Low-power control register SCKCR: System clock control register
Internal clock to peripheral modules
Bus master clock to CPU and DTC
Figure 20.1 Block Diagram of Clock Pulse Generator The frequency can be changed by means of the PLL circuit. Frequency changes are performed by software by settings in the low-power control register (LPWRCR) and system clock control register (SCKCR).
CPG0100B_000020020900
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Section 20 Clock Pulse Generator
20.1
Register Descriptions
The on-chip clock pulse generator has the following registers. * System clock control register (SCKCR) * Low-power control register (LPWRCR) 20.1.1 System Clock Control Register (SCKCR)
SCKCR performs clock output control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control.
Bit 7 Bit Name PSTOP Initial Value 0 R/W R/W Description Clock Output Disable Controls output. High-speed Mode, Medium-Speed Mode 0: output 1: Fixed high Sleep Mode 0: output 1: Fixed high Software Standby Mode 0: Fixed high 1: Fixed high Hardware Standby Mode 0: High impedance 1: High impedance 6 to 4 3 STCS All 0 0 R/W Reserved These bits are always read as 0. Frequency Multiplication Factor Switching Mode Select Selects the operation when the PLL circuit frequency multiplication factor is changed. 0: Specified multiplication factor is valid after transition to software standby mode 1: Specified multiplication factor is valid immediately after STC1 bit and STC0 bit are rewritten
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Section 20 Clock Pulse Generator Bit 2 1 0 Bit Name SCK2 SCK1 SCK0 Initial Value 0 0 0 R/W R/W R/W R/W Description System Clock Select 2 to 0 These bits select the bus master clock. 000: High-speed mode 001: Medium-speed clock is /2 010: Medium-speed clock is /4 011: Medium-speed clock is /8 100: Medium-speed clock is /16 101: Medium-speed clock is /32 11x: Setting prohibited Legend: x: Don't care
20.1.2
Bit 7 to 4 3, 2
Low-Power Control Register (LPWRCR)
Bit Name Initial Value All 0 All 0 R/W R/W Description Reserved The write value should always be 0. Reserved These bits can be read from and write to, but should not be set to 1.
1 0
STC1 STC0
0 0
R/W R/W
Frequency Multiplication Factor The STC bits specify the frequency multiplication factor of the PLL circuit. 00: x1 01: x2 10: x4 11: Setting prohibited
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Section 20 Clock Pulse Generator
20.2
Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. In either case, the input clock should not exceed 24 MHz. 20.2.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 20.2. Select the damping resistance Rd according to table 20.1. An AT-cut parallel-resonance crystal should be used.
CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 22 to 10 pF
Figure 20.2 Connection of Crystal Resonator (Example) Table 20.1 Damping Resistance Value
Frequency (MHz) Rd () 4 500 8 200 10 0 12 0 16 0 20 0 24 0
Figure 20.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 20.2.
CL XTAL L Rs EXTAL
C0
AT-cut parallel-resonance type
Figure 20.3 Crystal Resonator Equivalent Circuit
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Section 20 Clock Pulse Generator
Table 20.2 Crystal Resonator Characteristics
Frequency (MHz) RS max () C0 max (pF) 4 120 7 8 80 7 10 70 7 12 60 7 16 50 7 20 40 7 24 30 7
20.2.2
External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure 20.4. If the XTAL pin is left open, ensure that stray capacitance does not exceed 10 pF. When complementary clock is input to the XTAL pin, the external clock input should be fixed high in standby mode.
EXTAL XTAL Open
External clock input
(a) XTAL pin left open
EXTAL XTAL
External clock input
(b) Complementary clock input at XTAL pin
Figure 20.4 External Clock Input (Examples)
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Section 20 Clock Pulse Generator
Table 20.3 shows the input conditions for the external clock. Table 20.3 External Clock Input Conditions
VCC = 5.0 V 10% Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Symbol tEXL tEXH tEXr tEXf Min 15 15 Max 5 5 Unit ns ns ns ns Test Conditions Figure 20.5
tEXH
tEXL VCC x 0.5
EXTAL
tEXr
tEXf
Figure 20.5 External Clock Input Timing
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Section 20 Clock Pulse Generator
20.3
PLL Circuit
The PLL circuit multiplies the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set by the STC0 bit and the STC1 bit in LPWRCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin. When the multiplication factor of the PLL circuit is changed, the operation varies according to the setting of the STCS bit in SCKCR. When STCS = 0, the setting becomes valid after a transition to software standby mode. The transition time count is performed in accordance with the setting of bits STS2 to STS0 in SBYCR. For details on SBYCR, refer to section 21.1.1, Standby Control Register (SBYCR). The initial PLL circuit multiplication factor is 1. STS2 to STS0 are set to give the specified transition time. The target value is set in STC1 and STC0, and a transition is made to software standby mode. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS2 to STS0. 6. After the set transition time has elapsed, this LSI resumes operation using the target multiplication factor. If a PC break is set for the SLEEP instruction, software standby mode is entered and break exception handling is executed after the oscillation settling time. In this case, the instruction following the SLEEP instruction is executed after execution of the RTE instruction. When STCS = 1, this LSI operates on the changed multiplication factor immediately after bits STC1 and STC0 are rewritten. 1. 2. 3. 4. 5.
20.4
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32.
20.5
Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the clock supplied to the bus master by setting the bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from high-speed mode, or medium-speed clocks (/2, /4, /8, /16, /32).
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Section 20 Clock Pulse Generator
20.6
20.6.1
Usage Notes
Note on Crystal Resonator
As various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 20.6.2 Note on Board Design
When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator circuit, as shown in figure 20.6. This is to prevent induction from interfering with correct oscillation.
Avoid CL2 Signal A Signal B This LSI XTAL EXTAL CL1
Figure 20.6 Note on Board Design of Oscillator Circuit Figure 20.7 shows external circuitry recommended to be provided around the PLL circuit. Place oscillation settling capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Separate PLLVss from the other Vcc and Vss lines at the board power supply source, and be sure to insert bypass capacitors CB close to the pins.
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Section 20 Clock Pulse Generator
R1 = 3 k
C1 = 470 pF
PLLCAP
PLLVSS VCL VCC
CB = 0.1 F* CB = 0.1 F
VSS (Values are preliminary recommended values.) Note: * CB is laminated ceramic.
Figure 20.7 External Circuitry Recommended for PLL Circuit
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Section 20 Clock Pulse Generator
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Section 21 Power-Down Modes
Section 21 Power-Down Modes
In addition to the normal program execution state, this LSI has five power-down modes in which operation of the CPU and oscillator is halted and power consumption is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on. This LSI's operating modes are as follows: 1. 2. 3. 4. 5. 6. High-speed mode Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode
2. to 6. are power-down modes. Sleep mode is a CPU state, medium-speed mode is a CPU and bus master state, and module stop mode is an internal peripheral function (including bus masters other than the CPU) state. Some of these states can be combined. After a reset, the LSI is in high-speed mode. Figure 21.1 shows possible transitions between modes. Table 21.1 shows the conditions of transition made by the SLEEP instruction and recovery from power-down mode by an interrupt. Table 21.2 shows the internal states in each mode.
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Section 21 Power-Down Modes
Program-halted state STBY pin = Low Reset state Hardware standby mode
STBY pin = High, RES pin = Low
RES pin = High Program execution state SLEEP command High-speed mode (main clock) Any interrupt SLEEP command External interrupt* SSBY = 0 Sleep mode (main clock)
SCK2 to SCK0 = 0
SCK2 to SCK0 0
SSBY = 1 Software standby mode
Medium-speed mode (main clock)
: Transition after exception processing Notes:
: Low power dissipation mode
* NMI and IRQ5 to IRQ0 * When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * From any state except hardware standby mode, a transition to the reset state occurs when RES is driven low. * From any state, a transition to hardware standby mode occurs when STBY is driven low.
Figure 21.1 Mode Transition Diagram Table 21.1 Low Power Consumption Mode Transition Conditions
Status of Control Bit at Transition SSBY 0 1 State after Transition Invoked by SLEEP Command Sleep Software standby State after Transition Back from Low Power Mode Invoked by Interrupt High-speed/Medium-speed High-speed/Medium-speed
Pre-Transition State High-speed/ Medium-speed
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Section 21 Power-Down Modes
Table 21.2 LSI Internal States in Each Mode
Function System clock pulse generator CPU Instructions Registers MediumHigh-Speed Speed Operate Operate Operate Mediumspeed operation Operate Sleep Operate Halted (retained) Module Stop Operate High/ mediumspeed operation Operate Software Standby Halted Halted (retained) Hardware Standby Halted Halted (undefined)
External interrupts Peripheral functions
NMI IRQ5 to IRQ0 PBC DTC I/O TPU TMR PPG WDT SCI HCAN A/D RAM
Operate
Operate
Operate
Halted
Operate
Mediumspeed operation Operate Operate
Operate
Halted (retained) Operate Halted (retained)
Halted (retained) Retained Halted (retained)
Halted (reset) High impedance Halted (reset)
Operate Operate
Operate Operate
Operate Operate
Operate Operate
Operate Operate
Operate Halted* (reset/ retained) Operate
Halted (retained) Halted (reset)
Halted (reset) Halted (reset)
Operate
Mediumspeed operation Operate
Operate (DTC) Operate
Retained
Retained
SSU
Operate
Halted (reset)
Halted (reset)
Halted (reset)
Notes: Halted (retained) means that internal register values are retained. The internal state is in the operation suspended state. Halted (reset) means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). * The SCI's TDR, RDR, and SSR are halted (reset), and the other registers are halted (retained).
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Section 21 Power-Down Modes
21.1
Register Descriptions
Registers related to the power down mode are shown below. For details on the system clock control register (SCKCR), refer to section 20.1.1, System Clock Control Register (SCKCR). * * * * * System clock control register (SCKCR) Standby control register (SBYCR) Module stop control register A (MSTPCRA) Module stop control register B (MSTPCRB) Module stop control register C (MSTPCRC) Standby Control Register (SBYCR)
21.1.1
SBYCR is an 8-bit readable/writable register that performs software standby mode control.
Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby This bit specifies the transition mode after executing the SLEEP instruction 0: Shifts to sleep mode when the SLEEP instruction is executed 1: Shifts to software standby mode when the SLEEP instruction is executed This bit does not change when clearing the software standby mode by using external interrupts and shifting to normal operation. This bit should be written with 0 when clearing.
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Section 21 Power-Down Modes Bit 6 5 4 Bit Name STS2 STS1 STS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Standby Timer Select 2 to 0 These bits select the MCU wait time for clock settling when software standby mode is cancelled by an external interrupt. With a crystal oscillator (table 21.3), select a wait time of 8 ms (oscillation settling time) or more, depending on the operating frequency. With an external clock, select a wait time of 2 ms or more. 000: Standby time = 8,192 states 001: Standby time = 16,384 states 010: Standby time = 32,768 states 011: Standby time = 65,536 states 100: Standby time = 131,072 states 101: Standby time = 262,144 states 110: Reserved 111: Standby time = 16 states 3 2 to 0 1 All 0 R/W Reserved The write value should always be 0. Reserved These bits are always read as 0 and cannot be modified.
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Section 21 Power-Down Modes
21.1.2
Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)
MSTPCR is comprised of three 8-bit readable/writable registers, and performs module stop mode control. Setting a bit to 1 causes the corresponding module to enter module stop mode. Clearing the bit to 0 clears the module stop mode. * MSTPCRA
Bit 7 6 5 4 3 2 1 0 Bit Name MSTPA7* MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2* MSTPA1 MSTPA0 Initial Value 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W A/D converter 8-bit timer (TMR_3, TMR_2) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) 8-bit timer (TMR_1, TMR_0) Programmable pulse generator (PPG) Module
* MSTPCRB
Bit 7 6 5 4 3 2 1 0 Bit Name MSTPB7 MSTPB6* MSTPB5 MSTPB4* MSTPB3* MSTPB2* MSTPB1* MSTPB0* Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Serial communication interface 2 (SCI2) Module Serial communication interface 0 (SCI0)
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Section 21 Power-Down Modes
* MSTPCRC
Bit 7 6 5 4 3 2 1 0 Note: Bit Name MSTPC7* MSTPC6* MSTPC5* MSTPC4 MSTPC3 MSTPC2 MSTPC1* MSTPC0* * Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W PC break controller (PBC) Controller area network (HCAN) Synchronous serial communication unit (SSU) Module
MSTPA7 is a readable/writable bit with an initial value of 0. The write value should always be 0. MSTPA2, MSTPB6, MSTPB4 to MSTPB0, MSTPC7 to MSTPC5, MSTPC1, and MSTPC0 are readable/writable bits with an initial value of 1. The write value should always be 1.
21.2
Medium-Speed Mode
When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to mediumspeed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32) specified by the SCK2 to SCK0 bits. Bus masters (DTC) other than the CPU also operate in medium-speed mode. On-chip peripheral modules other than bus masters always operate on the high-speed clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored.
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Section 21 Power-Down Modes
When the pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer.
Figure 21.2 shows the timing for transition to and clearance of medium-speed mode.
Medium-speed mode , peripheral module clock
Bus master clock
Internal address bus
Internal write signal
21.3
21.3.1
Sleep Mode
Transition to Sleep Mode
If SLEEP instruction is executed when the SBYCR SSBY bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops, however the contents of the CPU's internal registers are retained. Other peripheral modules do not stop. 21.3.2 Clearing Sleep Mode
* Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or if interrupts other than NMI are masked by the CPU. * Exiting Sleep Mode by pin: Setting the pin low level selects the reset state. After the stipulated reset input duration, pin high level restart the CPU performing reset exception processing. driving the
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YBTS
SER
Sleep mode is cleared by any interrupt, or signals at the
SER
SER SER
YBTS
When the
SER
pin is driven low, a transition is made to hardware standby mode.
SCKCR
SCKCR
Figure 21.2 Medium-Speed Mode Transition and Clearance Timing
, or
pins.
Section 21 Power-Down Modes
* Exiting Sleep Mode by Pin: When the pin level is driven low, a transition is made to hardware standby mode.
21.4
21.4.1
Software Standby Mode
Transition to Software Standby Mode
A transition is made to software standby mode if the SLEEP instruction is executed when the SBYCR SSBY bit is set to 1. In this mode, the CPU, on-chip peripheral modules, and oscillator, all stop. However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral modules other than the SCI, SSU, HCAN, A/D converter, and the states of I/O ports, are retained. In this mode, the oscillator stops, and therefore power consumption is significantly reduced. 21.4.2 Clearing Software Standby Mode
* Clearing with an interrupt When an NMI or IRQ5 to IRQ0 interrupt request signal is input, clock oscillation starts, and after the time set in bits STS2 to STS0 in SBYCR has elapsed, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ5 to IRQ0 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ5 to IRQ0 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. * Clearing with the pin When the pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the pin must be held low pin goes high, the CPU begins reset exception until clock oscillation settles. When the handling. * Clearing with the pin When the pin is driven low, a transition is made to hardware standby mode.
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0QRI 5QRI
Software standby mode is cleared by an external interrupt (NMI pin, or pins pin or pin. means of the
SER
SER
YBTS
YBTS
YBTS
SER
YBTS YBTS SER
to
), or by
SER
Section 21 Power-Down Modes
21.4.3
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below. * Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation settling time). Table 21.3 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. * Using an External Clock The PLL circuit requires a time for settling. Set bits STS2 to STS0 so that the standby time is at least 2 ms(the oscillation settling time). Table 21.3 Oscillation Stabilization Time Settings
STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Note: 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 262,144 states Reserved 16 states* 24 20 16 12 10 8 6 4 MHz MHz MHz MHz MHz MHz MHz MHz Unit 0.34 0.41 0.51 0.68 0.8 0.68 0.82 1.0 1.4 2.7 5.5 0.7 1.6 3.3 6.6 0.8 2.0 4.1 8.2 1.0 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 8.2 ms
10.9 16.4
10.9 13.1 16.4 21.8 32.8 1.3 1.6 2.0 1.7 4.0 s
10.9 13.1 16.4 21.8 26.2 32.8 43.6 65.6
: Recommended time setting * Cannot be used in this LSI.
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Section 21 Power-Down Modes
21.4.4
Software Standby Mode Application Example
Figure 21.3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin.
Oscillator
NMI
NMIEG
SSBY
Software standby mode NMI exception (power-down mode) handling NMIEG = 1 SSBY = 1 SLEEP instruction
NMI exception handling Oscillation stabilization time tOSC2
Figure 21.3 Software Standby Mode Application Example
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Section 21 Power-Down Modes
21.5
21.5.1 When the
Hardware Standby Mode
Transition to Hardware Standby Mode pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before pin low. driving the Do not change the state of the mode pins (MD2 to MD0) while this LSI is in hardware standby mode. 21.5.2 Clearing Hardware Standby Mode
pin and the pin. When the Hardware standby mode is cleared by means of the pin is driven high while the pin is low, the reset state is set and clock oscillation is started. Ensure that the pin is held low until the clock oscillator settles (at least 8 msthe oscillation settling timewhen using a crystal oscillator). When the pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 21.5.3 Hardware Standby Mode Timings
Timing of Transition to Hardware Standby Mode 1. To retain RAM contents with the RAME bit set to 1 in SYSCR signal low at least 10 states before the signal goes low, as shown in Drive the figure 21.4. After has gone low, has to wait for at least 0 ns before becoming high.
STBY t1 10 tcyc RES t2 0 ns
Figure 21.4 Timing of Transition to Hardware Standby Mode
Rev. 3.00 Oct 04, 2005 page 512 of 598 REJ09B0155-0300
YBTS
SER
YBTS
SER
YBTS
SER
SER
YBTS
SER
SER
YBTS
YBTS
Section 21 Power-Down Modes
2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained does not have to be driven low as in the above case.
Timing of Recovery from Hardware Standby Mode
STBY t 100 ns RES tOSC1
Figure 21.5 Timing of Recovery from Hardware Standby Mode
21.6
Module Stop Mode
Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI*, HCAN, and A/D converter are retained. After reset clearance, all modules other than DTC are in module stop mode. When an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled. Note: * The internal states of some SCI registers are retained.
Rev. 3.00 Oct 04, 2005 page 513 of 598 REJ09B0155-0300
YBTS
signal low approximately 100 ns or more before Drive the power-on reset.
SER
SER
goes high to execute a
Section 21 Power-Down Modes
21.7
Clock Output Disabling Function
The output of the clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. Table 21.4 shows the state of the pin in each processing state. Table 21.4 Pin State in Each Processing State
Register Settings DDR 0 1 1 PSTOP x 0 1 Normal Mode High impedance output Fixed high Sleep Mode High impedance output Fixed high Software Standby Mode High impedance Fixed high Fixed high Hardware Standby Mode High impedance High impedance High impedance
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Section 21 Power-Down Modes
21.8
21.8.1
Usage Notes
I/O Port Status
In software standby mode, I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 21.8.2 Current Consumption during Oscillation Stabilization Wait Period
Current consumption increases during the oscillation settling wait period. 21.8.3 DTC Module Stop
Depending on the operating status of the DTC, MSTPA6 bit may not be set to 1. Setting of the DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, Data Transfer Controller (DTC). 21.8.4 On-Chip Peripheral Module Interrupt
Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. 21.8.5 Writing to MSTPCR
MSTPCR should only be written to by the CPU.
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Section 21 Power-Down Modes
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Section 22 List of Registers
Section 22 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * * 2. * * * Register addresses (address order) Registers are listed from the lower allocation addresses. When the address is 16-bit wide, the address of the upper byte is given in the list. Registers are classified by functional modules. The access size is indicated.
Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. Bit number in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * When registers consist of 16 bits, bits are described from the MSB side. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
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Section 22 List of Registers
22.1
Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register.
Register Name Master control register General status register Bit configuration register Mailbox configuration register Transmit wait register Transmit wait cancel register Transmit acknowledge register Abort acknowledge register Receive complete register Remote request register Interrupt register Mailbox interrupt mask register Interrupt mask register Receive error counter Transmit error counter Unread message status register Local acceptance filter mask L Local acceptance filter mask H Message control 0[1] Message control 0[2] Message control 0[3] Message control 0[4] Message control 0[5] Message control 0[6] Message control 0[7] Message control 0[8] Number Abbreviation of Bits Address* Module MCR GSR BCR MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR MBIMR IMR REC TEC UMSR LAFML LAFMH MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] 8 8 16 16 16 16 16 16 16 16 16 16 16 8 8 16 16 16 8 8 8 8 8 8 8 8 H'F800 H'F801 H'F802 H'F804 H'F806 H'F808 H'F80A H'F80C H'F80E H'F810 H'F812 H'F814 H'F816 H'F818 H'F819 H'F81A H'F81C H'F81E H'F820 H'F821 H'F822 H'F823 H'F824 H'F825 H'F826 H'F827 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
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Section 22 List of Registers Number Abbreviation of Bits Address* Module MC1[1] MC1[2] MC1[3] MC1[4] MC1[5] MC1[6] MC1[7] MC1[8] MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] MC3[1] MC3[2] MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] MC4[1] MC4[2] MC4[3] MC4[4] MC4[5] MC4[6] 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F828 H'F829 H'F82A H'F82B H'F82C H'F82D H'F82E H'F82F H'F830 H'F831 H'F832 H'F833 H'F834 H'F835 H'F836 H'F837 H'F838 H'F839 H'F83A H'F83B H'F83C H'F83D H'F83E H'F83F H'F840 H'F841 H'F842 H'F843 H'F844 H'F845 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Register Name Message control 1[1] Message control 1[2] Message control 1[3] Message control 1[4] Message control 1[5] Message control 1[6] Message control 1[7] Message control 1[8] Message control 2[1] Message control 2[2] Message control 2[3] Message control 2[4] Message control 2[5] Message control 2[6] Message control 2[7] Message control 2[8] Message control 3[1] Message control 3[2] Message control 3[3] Message control 3[4] Message control 3[5] Message control 3[6] Message control 3[7] Message control 3[8] Message control 4[1] Message control 4[2] Message control 4[3] Message control 4[4] Message control 4[5] Message control 4[6]
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Section 22 List of Registers Number Abbreviation of Bits Address* Module MC4[7] MC4[8] MC5[1] MC5[2] MC5[3] MC5[4] MC5[5] MC5[6] MC5[7] MC5[8] MC6[1] MC6[2] MC6[3] MC6[4] MC6[5] MC6[6] MC6[7] MC6[8] MC7[1] MC7[2] MC7[3] MC7[4] MC7[5] MC7[6] MC7[7] MC7[8] MC8[1] MC8[2] MC8[3] MC8[4] 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F846 H'F847 H'F848 H'F849 H'F84A H'F84B H'F84C H'F84D H'F84E H'F84F H'F850 H'F851 H'F852 H'F853 H'F854 H'F855 H'F856 H'F857 H'F858 H'F859 H'F85A H'F85B H'F85C H'F85D H'F85E H'F85F H'F860 H'F861 H'F862 H'F863 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Register Name Message control 4[7] Message control 4[8] Message control 5[1] Message control 5[2] Message control 5[3] Message control 5[4] Message control 5[5] Message control 5[6] Message control 5[7] Message control 5[8] Message control 6[1] Message control 6[2] Message control 6[3] Message control 6[4] Message control 6[5] Message control 6[6] Message control 6[7] Message control 6[8] Message control 7[1] Message control 7[2] Message control 7[3] Message control 7[4] Message control 7[5] Message control 7[6] Message control 7[7] Message control 7[8] Message control 8[1] Message control 8[2] Message control 8[3] Message control 8[4]
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Section 22 List of Registers Number Abbreviation of Bits Address* Module MC8[5] MC8[6] MC8[7] MC8[8] MC9[1] MC9[2] MC9[3] MC9[4] MC9[5] MC9[6] MC9[7] MC9[8] MC10[1] MC10[2] MC10[3] MC10[4] MC10[5] MC10[6] MC10[7] MC10[8] MC11[1] MC11[2] MC11[3] MC11[4] MC11[5] MC11[6] MC11[7] MC11[8] MC12[1] MC12[2] 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F864 H'F865 H'F866 H'F867 H'F868 H'F869 H'F86A H'F86B H'F86C H'F86D H'F86E H'F86F H'F870 H'F871 H'F872 H'F873 H'F874 H'F875 H'F876 H'F877 H'F878 H'F879 H'F87A H'F87B H'F87C H'F87D H'F87E H'F87F H'F880 H'F881 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Register Name Message control 8[5] Message control 8[6] Message control 8[7] Message control 8[8] Message control 9[1] Message control 9[2] Message control 9[3] Message control 9[4] Message control 9[5] Message control 9[6] Message control 9[7] Message control 9[8] Message control 10[1] Message control 10[2] Message control 10[3] Message control 10[4] Message control 10[5] Message control 10[6] Message control 10[7] Message control 10[8] Message control 11[1] Message control 11[2] Message control 11[3] Message control 11[4] Message control 11[5] Message control 11[6] Message control 11[7] Message control 11[8] Message control 12[1] Message control 12[2]
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Section 22 List of Registers Number Abbreviation of Bits Address* Module MC12[3] MC12[4] MC12[5] MC12[6] MC12[7] MC12[8] MC13[1] MC13[2] MC13[3] MC13[4] MC13[5] MC13[6] MC13[7] MC13[8] MC14[1] MC14[2] MC14[3] MC14[4] MC14[5] MC14[6] MC14[7] MC14[8] MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F882 H'F883 H'F884 H'F885 H'F886 H'F887 H'F888 H'F889 H'F88A H'F88B H'F88C H'F88D H'F88E H'F88F H'F890 H'F891 H'F892 H'F893 H'F894 H'F895 H'F896 H'F897 H'F898 H'F899 H'F89A H'F89B H'F89C H'F89D H'F89E H'F89F HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Register Name Message control 12[3] Message control 12[4] Message control 12[5] Message control 12[6] Message control 12[7] Message control 12[8] Message control 13[1] Message control 13[2] Message control 13[3] Message control 13[4] Message control 13[5] Message control 13[6] Message control 13[7] Message control 13[8] Message control 14[1] Message control 14[2] Message control 14[3] Message control 14[4] Message control 14[5] Message control 14[6] Message control 14[7] Message control 14[8] Message control 15[1] Message control 15[2] Message control 15[3] Message control 15[4] Message control 15[5] Message control 15[6] Message control 15[7] Message control 15[8]
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Section 22 List of Registers Number Abbreviation of Bits Address* Module MD0[1] MD0[2] MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] MD1[1] MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] MD2[1] MD2[2] MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F8B0 H'F8B1 H'F8B2 H'F8B3 H'F8B4 H'F8B5 H'F8B6 H'F8B7 H'F8B8 H'F8B9 H'F8BA H'F8BB H'F8BC H'F8BD H'F8BE H'F8BF H'F8C0 H'F8C1 H'F8C2 H'F8C3 H'F8C4 H'F8C5 H'F8C6 H'F8C7 H'F8C8 H'F8C9 H'F8CA H'F8CB H'F8CC H'F8CD HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Register Name Message data 0[1] Message data 0[2] Message data 0[3] Message data 0[4] Message data 0[5] Message data 0[6] Message data 0[7] Message data 0[8] Message data 1[1] Message data 1[2] Message data 1[3] Message data 1[4] Message data 1[5] Message data 1[6] Message data 1[7] Message data 1[8] Message data 2[1] Message data 2[2] Message data 2[3] Message data 2[4] Message data 2[5] Message data 2[6] Message data 2[7] Message data 2[8] Message data 3[1] Message data 3[2] Message data 3[3] Message data 3[4] Message data 3[5] Message data 3[6]
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Section 22 List of Registers Number Abbreviation of Bits Address* Module MD3[7] MD3[8] MD4[1] MD4[2] MD4[3] MD4[4] MD4[5] MD4[6] MD4[7] MD4[8] MD5[1] MD5[2] MD5[3] MD5[4] MD5[5] MD5[6] MD5[7] MD5[8] MD6[1] MD6[2] MD6[3] MD6[4] MD6[5] MD6[6] MD6[7] MD6[8] MD7[1] MD7[2] MD7[3] MD7[4] 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F8CE H'F8CF H'F8D0 H'F8D1 H'F8D2 H'F8D3 H'F8D4 H'F8D5 H'F8D6 H'F8D7 H'F8D8 H'F8D9 H'F8DA H'F8DB H'F8DC H'F8DD H'F8DE H'F8DF H'F8E0 H'F8E1 H'F8E2 H'F8E3 H'F8E4 H'F8E5 H'F8E6 H'F8E7 H'F8E8 H'F8E9 H'F8EA H'F8EB HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Register Name Message data 3[7] Message data 3[8] Message data 4[1] Message data 4[2] Message data 4[3] Message data 4[4] Message data 4[5] Message data 4[6] Message data 4[7] Message data 4[8] Message data 5[1] Message data 5[2] Message data 5[3] Message data 5[4] Message data 5[5] Message data 5[6] Message data 5[7] Message data 5[8] Message data 6[1] Message data 6[2] Message data 6[3] Message data 6[4] Message data 6[5] Message data 6[6] Message data 6[7] Message data 6[8] Message data 7[1] Message data 7[2] Message data 7[3] Message data 7[4]
Rev. 3.00 Oct 04, 2005 page 524 of 598 REJ09B0155-0300
Section 22 List of Registers Number Abbreviation of Bits Address* Module MD7[5] MD7[6] MD7[7] MD7[8] MD8[1] MD8[2] MD8[3] MD8[4] MD8[5] MD8[6] MD8[7] MD8[8] MD9[1] MD9[2] MD9[3] MD9[4] MD9[5] MD9[6] MD9[7] MD9[8] MD10[1] MD10[2] MD10[3] MD10[4] MD10[5] MD10[6] MD10[7] MD10[8] MD11[1] MD11[2] 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F8EC H'F8ED H'F8EE H'F8EF H'F8F0 H'F8F1 H'F8F2 H'F8F3 H'F8F4 H'F8F5 H'F8F6 H'F8F7 H'F8F8 H'F8F9 H'F8FA H'F8FB H'F8FC H'F8FD H'F8FE H'F8FF H'F900 H'F901 H'F902 H'F903 H'F904 H'F905 H'F906 H'F907 H'F908 H'F909 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Register Name Message data 7[5] Message data 7[6] Message data 7[7] Message data 7[8] Message data 8[1] Message data 8[2] Message data 8[3] Message data 8[4] Message data 8[5] Message data 8[6] Message data 8[7] Message data 8[8] Message data 9[1] Message data 9[2] Message data 9[3] Message data 9[4] Message data 9[5] Message data 9[6] Message data 9[7] Message data 9[8] Message data 10[1] Message data 10[2] Message data 10[3] Message data 10[4] Message data 10[5] Message data 10[6] Message data 10[7] Message data 10[8] Message data 11[1] Message data 11[2]
Rev. 3.00 Oct 04, 2005 page 525 of 598 REJ09B0155-0300
Section 22 List of Registers Number Abbreviation of Bits Address* Module MD11[3] MD11[4] MD11[5] MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] MD12[4] MD12[5] MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1] MD14[2] MD14[3] MD14[4] MD14[5] MD14[6] MD14[7] MD14[8] 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F90A H'F90B H'F90C H'F90D H'F90E H'F90F H'F910 H'F911 H'F912 H'F913 H'F914 H'F915 H'F916 H'F917 H'F918 H'F919 H'F91A H'F91B H'F91C H'F91D H'F91E H'F91F H'F920 H'F921 H'F922 H'F923 H'F924 H'F925 H'F926 H'F927 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Register Name Message data 11[3] Message data 11[4] Message data 11[5] Message data 11[6] Message data 11[7] Message data 11[8] Message data 12[1] Message data 12[2] Message data 12[3] Message data 12[4] Message data 12[5] Message data 12[6] Message data 12[7] Message data 12[8] Message data 13[1] Message data 13[2] Message data 13[3] Message data 13[4] Message data 13[5] Message data 13[6] Message data 13[7] Message data 13[8] Message data 14[1] Message data 14[2] Message data 14[3] Message data 14[4] Message data 14[5] Message data 14[6] Message data 14[7] Message data 14[8]
Rev. 3.00 Oct 04, 2005 page 526 of 598 REJ09B0155-0300
Section 22 List of Registers Number Abbreviation of Bits Address* Module MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8] HCANMON SSCRH_0 SSCRL_0 SSMR_0 SSER_0 SSSR_0 SSTDR0_0 SSTDR1_0 SSTDR2_0 SSTDR3_0 SSRDR0_0 SSRDR1_0 SSRDR2_0 SSRDR3_0 SSCRH_1 SSCRL_1 SSMR_1 SSER_1 SSSR_1 SSTDR0_1 SSTDR1_1 SSTDR2_1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F928 H'F929 H'F92A H'F92B H'F92C H'F92D H'F92E H'F92F H'FA00 H'FB00 H'FB01 H'FB02 H'FB03 H'FB04 H'FB06 H'FB07 H'FB08 H'FB09 H'FB0A H'FB0B H'FB0C H'FB0D H'FB10 H'FB11 H'FB12 H'FB13 H'FB14 H'FB16 H'FB17 H'FB18 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_0 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Register Name Message data 15[1] Message data 15[2] Message data 15[3] Message data 15[4] Message data 15[5] Message data 15[6] Message data 15[7] Message data 15[8] HCAN monitor register SS control register H_0 SS control register L_0 SS mode register_0 SS enable register_0 SS status register_0 SS transmit data register 0_0 SS transmit data register 1_0 SS transmit data register 2_0 SS transmit data register 3_0 SS receive data register 0_0 SS receive data register 1_0 SS receive data register 2_0 SS receive data register 3_0 SS control register H_1 SS control register L_1 SS mode register_1 SS enable register_1 SS status register_1 SS transmit data register 0_1 SS transmit data register 1_1 SS transmit data register 2_1
Rev. 3.00 Oct 04, 2005 page 527 of 598 REJ09B0155-0300
Section 22 List of Registers Number Abbreviation of Bits Address* Module SSTDR3_1 SSRDR0_1 SSRDR1_1 SSRDR2_1 SSRDR3_1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 32 32 8 8 8 8 H'FB19 H'FB1A H'FB1B H'FB1C H'FB1D H'FB40 H'FDC0 H'FDC1 H'FDC2 H'FDC3 H'FDC4 H'FDC5 H'FDC6 H'FDC7 H'FDC8 H'FDC9 H'FDE4 H'FDE5 H'FDE6 H'FDE7 H'FDE8 H'FDE9 H'FDEA H'FDEC H'FE00 H'FE04 H'FE08 H'FE09 H'FE12 H'FE13 SSU_1 SSU_1 SSU_1 SSU_1 SSU_1 PORT TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 Data Access Width State 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name SS transmit data register 3_1 SS receive data register 0_1 SS receive data register 1_1 SS receive data register 2_1 SS receive data register 3_1
Port D realtime input data register PDRTIDR Timer control register_2 Timer control register_3 Timer control/status register_2 Timer control/status register_3 Timer constant register A_2 Timer constant register A_3 Timer constant register B_2 Timer constant register B_3 Timer counter_2 Timer counter_3 Standby control register System control register System clock control register Mode control register Module stop control register A Module stop control register B Module stop control register C Low-power control register Break address register A Break address register B Break control register A Break control register B IRQ sense control register H IRQ sense control register L TCR_2 TCR_3 TCSR_2 TCSR_3 TCORA_2 TCORA_3 TCORB_2 TCORB_3 TCNT_2 TCNT_3 SBYCR SYSCR SCKCR MDCR MSTPCRA MSTPCRB MSTPCRC LPWRCR BARA BARB BCRA BCRB ISCRH ISCRL
SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 PBC PBC PBC PBC INT INT 32 32 8 8 8 8
Rev. 3.00 Oct 04, 2005 page 528 of 598 REJ09B0155-0300
Section 22 List of Registers Number Abbreviation of Bits Address* Module IER ISR DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTVECR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL P1DDR P3DDR P7DDR PADDR PBDDR PCDDR PDDDR PFDDR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE14 H'FE15 H'FE16 H'FE17 H'FE18 H'FE19 H'FE1A H'FE1B H'FE1C H'FE1F H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE32 H'FE36 H'FE39 H'FE3A H'FE3B H'FE3C H'FE3E H'FE40 H'FE41 INT INT DTC DTC DTC DTC DTC DTC DTC DTC PPG PPG PPG PPG PPG PPG PPG PPG PPG PPG PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Data Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name IRQ enable register IRQ status register DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC enable register F DTC enable register G DTC vector register PPG output control register PPG output mode register Next data enable register H Next data enable register L Output data register H Output data register L Next data register H Next data register L Next data register H Next data register L Port 1 data direction register Port 3 data direction register Port 7 data direction register Port A data direction register Port B data direction register Port C data direction register Port D data direction register Port F data direction register
Port A pull-up MOS control register PAPCR Port B pull-up MOS control register PBPCR
Rev. 3.00 Oct 04, 2005 page 529 of 598 REJ09B0155-0300
Section 22 List of Registers Number Abbreviation of Bits Address* Module 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE42 H'FE43 H'FE46 H'FE47 H'FE48 H'FE49 H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8B H'FE8C H'FE8D H'FE8E H'FE8F H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 PORT PORT PORT PORT PORT PORT TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 Data Access Width State 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name
Port C pull-up MOS control register PCPCR Port D pull-up MOS control register PDPCR Port 3 open drain control register Port A open drain control register Port B open drain control register Port C open drain control register Timer control register_3 Timer mode register_3 Timer I/O control register H_3 Timer I/O control register L_3 Timer interrupt enable register_3 Timer status register_3 Timer counter H_3 Timer counter L_3 Timer general register AH_3 Timer general register AL_3 Timer general register BH_3 Timer general register BL_3 Timer general register CH_3 Timer general register CL_3 Timer general register DH_3 Timer general register DL_3 Timer control register_4 Timer mode register_4 Timer I/O control register_4 Timer interrupt enable register_4 Timer status register_4 Timer counter H_4 Timer counter L_4 Timer general register AH_4 P3ODR PAODR PBODR PCODR TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNTH_3 TCNTL_3 TGRAH_3 TGRAL_3 TGRBH_3 TGRBL_3 TGRCH_3 TGRCL_3 TGRDH_3 TGRDL_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNTH_4 TCNTL_4 TGRAH_4
Rev. 3.00 Oct 04, 2005 page 530 of 598 REJ09B0155-0300
Section 22 List of Registers Number Abbreviation of Bits Address* Module TGRAL_4 TGRBH_4 TGRBL_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNTH_5 TCNTL_5 TGRAH_5 TGRAL_5 TGRBH_5 TGRBL_5 TSTR TSYR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRM RAMER P1DR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE99 H'FE9A H'FE9B H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB H'FEB0 H'FEB1 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC9 H'FECA H'FECC H'FEDB H'FF00 TPU_4 TPU_4 TPU_4 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Timer general register AL_4 Timer general register BH_4 Timer general register BL_4 Timer control register_5 Timer mode register_5 Timer I/O control register_5 Timer interrupt enable register_5 Timer status register_5 Timer counter H_5 Timer counter L_5 Timer general register AH_5 Timer general register AL_5 Timer general register BH_5 Timer general register BL_5 Timer start register Timer synchro register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register J Interrupt priority register K Interrupt priority register M RAM emulation register Port 1 data register
TPU 16 common TPU 16 common INT INT INT INT INT INT INT INT INT INT INT ROM PORT 8 8 8 8 8 8 8 8 8 8 8 8 8
Rev. 3.00 Oct 04, 2005 page 531 of 598 REJ09B0155-0300
Section 22 List of Registers Number Abbreviation of Bits Address* Module P3DR P7DR PADR PBDR PCDR PDDR PFDR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNTH_0 TCNTL_0 TGRAH_0 TGRAL_0 TGRBH_0 TGRBL_0 TGRCH_0 TGRCL_0 TGRDH_0 TGRDL_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNTH_1 TCNTL_1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF02 H'FF06 H'FF09 H'FF0A H'FF0B H'FF0C H'FF0E H'FF10 H'FF11 H'FF12 H'FF13 H'FF14 H'FF15 H'FF16 H'FF17 H'FF18 H'FF19 H'FF1A H'FF1B H'FF1C H'FF1D H'FF1E H'FF1F H'FF20 H'FF21 H'FF22 H'FF24 H'FF25 H'FF26 H'FF27 PORT PORT PORT PORT PORT PORT PORT TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 Data Access Width State 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Port 3 data register Port 7 data register Port A data register Port B data register Port C data register Port D data register Port F data register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter H_0 Timer counter L_0 Timer general register AH_0 Timer general register AL_0 Timer general register BH_0 Timer general register BL_0 Timer general register CH_0 Timer general register CL_0 Timer general register DH_0 Timer general register DL_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 Timer counter H_1 Timer counter L_1
Rev. 3.00 Oct 04, 2005 page 532 of 598 REJ09B0155-0300
Section 22 List of Registers Number Abbreviation of Bits Address* Module TGRAH_1 TGRAL_1 TGRBH_1 TGRBL_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNTH_2 TCNTL_2 TGRAH_2 TGRAL_2 TGRBH_2 TGRBL_2 TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 TCSR_0 TCNT_0 RSTCSR SMR_0 BRR_0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF28 H'FF29 H'FF2A H'FF2B H'FF30 H'FF31 H'FF32 H'FF34 H'FF35 H'FF36 H'FF37 H'FF38 H'FF39 H'FF3A H'FF3B H'FF68 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D H'FF6E H'FF6F H'FF70 H'FF71 H'FF74 H'FF75 H'FF77 H'FF78 H'FF79 TPU_1 TPU_1 TPU_1 TPU_1 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 WDT_0 WDT_0 WDT SCI_0 SCI_0 Data Access Width State 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 16 16 16 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Timer general register AH_1 Timer general register AL_1 Timer general register BH_1 Timer general register BL_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counterH_2 Timer counter L_2 Timer general register AH_2 Timer general register AL_2 Timer general register BH_2 Timer general register BL_2 Timer control register_0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0 Time constant register B_1 Timer counter_0 Timer counter_1 Timer control/status register_0 Timer counter_0 Reset control/status register Serial mode register_0 Bit rate register_0
Rev. 3.00 Oct 04, 2005 page 533 of 598 REJ09B0155-0300
Section 22 List of Registers Number Abbreviation of Bits Address* Module SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR FLMCR1 FLMCR2 EBR1 EBR2 PORT1 PORT3 PORT4 PORT7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFB0 H'FFB2 H'FFB3 H'FFB6 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 A/D A/D A/D A/D A/D A/D A/D A/D A/D A/D ROM ROM ROM ROM PORT PORT PORT PORT Data Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Smart card mode register_0 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Smart card mode register_2 A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Port 1 register Port 3 register Port 4 register Port 7 register
Rev. 3.00 Oct 04, 2005 page 534 of 598 REJ09B0155-0300
Section 22 List of Registers Number Abbreviation of Bits Address* Module PORT9 PORTA PORTB PORTC PORTD PORTF 8 8 8 8 8 8 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBE PORT PORT PORT PORT PORT PORT Data Access Width State 8 8 8 8 8 8 2 2 2 2 2 2
Register Name Port 9 register Port A register Port B register Port C register Port D register Port F register Note: *
Lower 16 bits of the address.
Rev. 3.00 Oct 04, 2005 page 535 of 598 REJ09B0155-0300
Section 22 List of Registers
22.2
Register Bits
The bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row.
Abbreviation Bit 7 MCR GSR BCR MCR7 BCR7 BCR15 MBCR MBCR7
Bit 6 BCR6 BCR14 MBCR6
Bit 5 MCR5 BCR5 BCR13 MBCR5
Bit 4 BCR4 BCR12 MBCR4
Bit 3 GSR3 BCR3 BCR11 MBCR3
Bit 2 MCR2 GSR2 BCR2 BCR10 MBCR2
Bit 1 MCR1 GSR1 BCR1 BCR9 MBCR1
Bit 0 MCR0 GSR0 BCR0 BCR8 MBCR8 TXPR8 TXCR8 TXACK8 ABACK8 RXPR0 RXPR8 RFPR0 RFPR8 IRR0 IRR8 MBIMR0 MBIMR8 IMR8 Bit 0 Bit 0
Module HCAN
MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 TXPR TXPR7 TXPR15 TXCR TXCR7 TXCR15 TXACK TXACK7 TXPR6 TXPR14 TXCR6 TXCR14 TXACK6 TXPR5 TXPR13 TXCR5 TXCR13 TXACK5 TXPR4 TXPR12 TXCR4 TXCR12 TXACK4 TXPR3 TXPR11 TXCR3 TXCR11 TXACK3 TXPR2 TXPR10 TXCR2 TXCR10 TXACK2 TXPR1 TXPR9 TXCR1 TXCR9 TXACK1
TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 ABACK ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1
ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 RXPR RXPR7 RXPR15 RFPR RFPR7 RFPR15 IRR IRR7 MBIMR MBIMR7 RXPR6 RXPR14 RFPR6 RFPR14 IRR6 MBIMR6 RXPR5 RXPR13 RFPR5 RFPR13 IRR5 MBIMR5 RXPR4 RXPR12 RFPR4 RFPR12 IRR4 IRR12 MBIMR4 RXPR3 RXPR11 RFPR3 RFPR11 IRR3 MBIMR3 RXPR2 RXPR10 RFPR2 RFPR10 IRR2 MBIMR2 RXPR1 RXPR9 RFPR1 RFPR9 IRR1 IRR9 MBIMR1
MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 IMR IMR7 REC TEC Bit 7 Bit 7 IMR6 Bit 6 Bit 6 IMR5 Bit 5 Bit 5 IMR4 IMR12 Bit 4 Bit 4 IMR3 Bit 3 Bit 3 IMR2 Bit 2 Bit 2 IMR1 IMR9 Bit 1 Bit 1
Rev. 3.00 Oct 04, 2005 page 536 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 UMSR UMSR7
Bit 6 UMSR6
Bit 5 UMSR5
Bit 4 UMSR4
Bit 3 UMSR3
Bit 2 UMSR2
Bit 1 UMSR1
Bit 0 UMSR0 UMSR8 LAFML0 LAFML8 LAFMH0 LAFMH8 DLC0 ID-16 ID-21 ID-0 ID-8 DLC0 ID-16 ID-21 ID-0 ID-8 DLC0 ID-16 ID-21 ID-0 ID-8
Module HCAN
UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 LAFML LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1
LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFMH LAFMH7 LAFMH6 LAFMH5 LAFMH1
LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] MC1[1] MC1[2] MC1[3] MC1[4] MC1[5] MC1[6] MC1[7] MC1[8] MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] ID-20 ID-28 ID-7 ID-15 ID-20 ID-28 ID-7 ID-15 ID-20 ID-28 ID-7 ID-15 ID-19 ID-27 ID-6 ID-14 ID-19 ID-27 ID-6 ID-14 ID-19 ID-27 ID-6 ID-14 ID-18 ID-26 ID-5 ID-13 ID-18 ID-26 ID-5 ID-13 ID-18 ID-26 ID-5 ID-13 RTR ID-25 ID-4 ID-12 RTR ID-25 ID-4 ID-12 RTR ID-25 ID-4 ID-12 DLC3 IDE ID-24 ID-3 ID-11 DLC3 IDE ID-24 ID-3 ID-11 DLC3 IDE ID-24 ID-3 ID-11 DLC2 ID-23 ID-2 ID-10 DLC2 - ID-23 ID-2 ID-10 DLC2 ID-23 ID-2 ID-10 DLC1 ID-17 ID-22 ID-1 ID-9 DLC1 ID-17 ID-22 ID-1 ID-9 DLC1 ID-17 ID-22 ID-1 ID-9
Rev. 3.00 Oct 04, 2005 page 537 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 MC3[1] MC3[2] MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] MC4[1] MC4[2] MC4[3] MC4[4] MC4[5] MC4[6] MC4[7] MC4[8] MC5[1] MC5[2] MC5[3] MC5[4] MC5[5] MC5[6] MC5[7] MC5[8] MC6[1] MC6[2] MC6[3] MC6[4] MC6[5] MC6[6] ID-20 ID-28 ID-7 ID-15 ID-20 ID-28 ID-7 ID-15 ID-20 ID-28 ID-7 ID-15 ID-20 ID-28
Bit 6 ID-19 ID-27 ID-6 ID-14 ID-19 ID-27 ID-6 ID-14 ID-19 ID-27 ID-6 ID-14 ID-19 ID-27
Bit 5 ID-18 ID-26 ID-5 ID-13 ID-18 ID-26 ID-5 ID-13 ID-18 ID-26 ID-5 ID-13 ID-18 ID-26
Bit 4 RTR ID-25 ID-4 ID-12 RTR ID-25 ID-4 ID-12 RTR ID-25 ID-4 ID-12 RTR ID-25
Bit 3 DLC3 IDE ID-24 ID-3 ID-11 DLC3 IDE ID-24 ID-3 ID-11 DLC3 IDE ID-24 ID-3 ID-11 DLC3 IDE ID-24
Bit 2 DLC2 ID-23 ID-2 ID-10 DLC2 ID-23 ID-2 ID-10 DLC2 ID-23 ID-2 ID-10 DLC2 ID-23
Bit 1 DLC1 ID-17 ID-22 ID-1 ID-9 DLC1 ID-17 ID-22 ID-1 ID-9 DLC1 ID-17 ID-22 ID-1 ID-9 DLC1 ID-17 ID-22
Bit 0 DLC0 ID-16 ID-21 ID-0 ID-8 DLC0 ID-16 ID-21 ID-0 ID-8 DLC0 ID-16 ID-21 ID-0 ID-8 DLC0 ID-16 ID-21
Module HCAN
Rev. 3.00 Oct 04, 2005 page 538 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 MC6[7] MC6[8] MC7[1] MC7[2] MC7[3] MC7[4] MC7[5] MC7[6] MC7[7] MC7[8] MC8[1] MC8[2] MC8[3] MC8[4] MC8[5] MC8[6] MC8[7] MC8[8] MC9[1] MC9[2] MC9[3] MC9[4] MC9[5] MC9[6] MC9[7] MC9[8] MC10[1] MC10[2] MC10[3] MC10[4] ID-7 ID-15 ID-20 ID-28 ID-7 ID-15 ID-20 ID-28 ID-7 ID-15 ID-20 ID-28 ID-7 ID-15
Bit 6 ID-6 ID-14 ID-19 ID-27 ID-6 ID-14 ID-19 ID-27 ID-6 ID-14 ID-19 ID-27 ID-6 ID-14
Bit 5 ID-5 ID-13 ID-18 ID-26 ID-5 ID-13 ID-18 ID-26 ID-5 ID-13 ID-18 ID-26 ID-5 ID-13
Bit 4 ID-4 ID-12 RTR ID-25 ID-4 ID-12 RTR ID-25 ID-4 ID-12 RTR ID-25 ID-4 ID-12
Bit 3 ID-3 ID-11 DLC3 IDE ID-24 ID-3 ID-11 DLC3 IDE ID-24 ID-3 ID-11 DLC3 IDE ID-24 ID-3 ID-11 DLC3
Bit 2 ID-2 ID-10 DLC2 ID-23 ID-2 ID-10 DLC2 ID-23 ID-2 ID-10 DLC2 ID-23 ID-2 ID-10 DLC2
Bit 1 ID-1 ID-9 DLC1 ID-17 ID-22 ID-1 ID-9 DLC1 ID-17 ID-22 ID-1 ID-9 DLC1 ID-17 ID-22 ID-1 ID-9 DLC1
Bit 0 ID-0 ID-8 DLC0 ID-16 ID-21 ID-0 ID-8 DLC0 ID-16 ID-21 ID-0 ID-8 DLC0 ID-16 ID-21 ID-0 ID-8 DLC0
Module HCAN
Rev. 3.00 Oct 04, 2005 page 539 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 MC10[5] MC10[6] MC10[7] MC10[8] MC11[1] MC11[2] MC11[3] MC11[4] MC11[5] MC11[6] MC11[7] MC11[8] MC12[1] MC12[2] MC12[3] MC12[4] MC12[5] MC12[6] MC12[7] MC12[8] MC13[1] MC13[2] MC13[3] MC13[4] MC13[5] MC13[6] MC13[7] MC13[8] MC14[1] MC14[2] ID-20 ID-28 ID-7 ID-15 ID-20 ID-28 ID-7 ID-15 ID-20 ID-28 ID-7 ID-15 ID-20 ID-28 ID-7 ID-15
Bit 6 ID-19 ID-27 ID-6 ID-14 ID-19 ID-27 ID-6 ID-14 ID-19 ID-27 ID-6 ID-14 ID-19 ID-27 ID-6 ID-14
Bit 5 ID-18 ID-26 ID-5 ID-13 ID-18 ID-26 ID-5 ID-13 ID-18 ID-26 ID-5 ID-13 ID-18 ID-26 ID-5 ID-13
Bit 4 RTR ID-25 ID-4 ID-12 RTR ID-25 ID-4 ID-12 RTR ID-25 ID-4 ID-12 RTR ID-25 ID-4 ID-12
Bit 3 IDE ID-24 ID-3 ID-11 DLC3 IDE ID-24 ID-3 ID-11 DLC3 IDE ID-24 ID-3 ID-11 DLC3 IDE ID-24 ID-3 ID-11 DLC3
Bit 2 ID-23 ID-2 ID-10 DLC2 - ID-23 ID-2 ID-10 DLC2 ID-23 ID-2 ID-10 DLC2 ID-23 ID-2 ID-10 DLC2
Bit 1 ID-17 ID-22 ID-1 ID-9 DLC1 ID-17 ID-22 ID-1 ID-9 DLC1 ID-17 ID-22 ID-1 ID-9 DLC1 ID-17 ID-22 ID-1 ID-9 DLC1
Bit 0 ID-16 ID-21 ID-0 ID-8 DLC0 ID-16 ID-21 ID-0 ID-8 DLC0 ID-16 ID-21 ID-0 ID-8 DLC0 ID-16 ID-21 ID-0 ID-8 DLC0
Module HCAN
Rev. 3.00 Oct 04, 2005 page 540 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 MC14[3] MC14[4] MC14[5] MC14[6] MC14[7] MC14[8] MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] MD0[1] MD0[2] MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] MD1[1] MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] ID-20 ID-28 ID-7 ID-15 ID-20 ID-28 ID-7 ID-15 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7
Bit 6 ID-19 ID-27 ID-6 ID-14 ID-19 ID-27 ID-6 ID-14 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6
Bit 5 ID-18 ID-26 ID-5 ID-13 ID-18 ID-26 ID-5 ID-13 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5
Bit 4 RTR ID-25 ID-4 ID-12 RTR ID-25 ID-4 ID-12 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4
Bit 3 IDE ID-24 ID-3 ID-11 DLC3 IDE ID-24 ID-3 ID-11 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3
Bit 2 ID-23 ID-2 ID-10 DLC2 ID-23 ID-2 ID-10 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2
Bit 1 ID-17 ID-22 ID-1 ID-9 DLC1 ID-17 ID-22 ID-1 ID-9 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1
Bit 0 ID-16 ID-21 ID-0 ID-8 DLC0 ID-16 ID-21 ID-0 ID-8 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Module HCAN
Rev. 3.00 Oct 04, 2005 page 541 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 MD2[1] MD2[2] MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] MD4[1] MD4[2] MD4[3] MD4[4] MD4[5] MD4[6] MD4[7] MD4[8] MD5[1] MD5[2] MD5[3] MD5[4] MD5[5] MD5[6] Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7
Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6
Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5
Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4
Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3
Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2
Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1
Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Module HCAN
Rev. 3.00 Oct 04, 2005 page 542 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 MD5[7] MD5[8] MD6[1] MD6[2] MD6[3] MD6[4] MD6[5] MD6[6] MD6[7] MD6[8] MD7[1] MD7[2] MD7[3] MD7[4] MD7[5] MD7[6] MD7[7] MD7[8] MD8[1] MD8[2] MD8[3] MD8[4] MD8[5] MD8[6] MD8[7] MD8[8] MD9[1] MD9[2] MD9[3] MD9[4] Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7
Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6
Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5
Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4
Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3
Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2
Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1
Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Module HCAN
Rev. 3.00 Oct 04, 2005 page 543 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 MD9[5] MD9[6] MD9[7] MD9[8] MD10[1] MD10[2] MD10[3] MD10[4] MD10[5] MD10[6] MD10[7] MD10[8] MD11[1] MD11[2] MD11[3] MD11[4] MD11[5] MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] MD12[4] MD12[5] MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7
Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6
Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5
Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4
Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3
Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2
Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1
Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Module HCAN
Rev. 3.00 Oct 04, 2005 page 544 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1] MD14[2] MD14[3] MD14[4] MD14[5] MD14[6] MD14[7] MD14[8] MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8] HCAN MON Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 RXDIE
Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 TxSTP
Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5
Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4
Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3
Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2
Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 TxD
Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 RxD
Module HCAN
Rev. 3.00 Oct 04, 2005 page 545 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 SSCRH _0 SSCRL _0 SSMR _0 SSER _0 SSSR _0 SSTDR0 _0 SSTDR1 _0 SSTDR2 _0 SSTDR3 _0 MSS MLS TE Bit 7 Bit 7 Bit 7 Bit 7
Bit 6 BIDE CPOS RE ORER Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6
Bit 5 SRES CPHS Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5
Bit 4 SOL Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4
Bit 3 SOLP TEIE TEND Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3
Bit 2 SCKS CKS2 TIE TDRE Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2
Bit 1 CSS1 DATS1 CKS1 RIE RDRF Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1
Bit 0 CSS0 DATS0 CKS0 CEIE CE Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Module SSU_0
SSRDR0 Bit 7 _0 SSRDR1 Bit 7 _0 SSRDR2 Bit 7 _0 SSRDR3 Bit 7 _0
Rev. 3.00 Oct 04, 2005 page 546 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 SSCRH _1 SSCRL _1 MSS
Bit 6 BIDE CPOS RE ORER Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 CMIEA CMIEA CMFA CMFA Bit 6 Bit 6
Bit 5 SRES CPHS Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 OVIE OVIE OVF OVF Bit 5 Bit 5
Bit 4 SOL Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 CCLR1 CCLR1 ADTE Bit 4 Bit 4
Bit 3 SOLP TEIE TEND Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 CCLR0 CCLR0 OS3 OS3 Bit 3 Bit 3
Bit 2 SCKS CKS2 TIE TDRE Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 CKS2 CKS2 OS2 OS2 Bit 2 Bit 2
Bit 1 CSS1 DATS1 CKS1 RIE RDRF Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 CKS1 CKS1 OS1 OS1 Bit 1 Bit 1
Bit 0 CSS0 DATS0 CKS0 CEIE CE Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 CKS0 CKS0 OS0 OS0 Bit 0 Bit 0
Module SSU_1
SSMR_1 MLS SSER_1 SSSR_1 SSTDR0 _1 SSTDR1 _1 SSTDR2 _1 SSTDR3 _1 TE Bit 7 Bit 7 Bit 7 Bit 7
SSRDR0 Bit 7 _1 SSRDR1 Bit 7 _1 SSRDR2 Bit 7 _1 SSRDR3 Bit 7 _1 PDRTIDR Bit 7 TCR_2 TCR_3 TCSR_2 TCSR_3 TCORA _2 TCORA _3 CMIEB CMIEB CMFB CMFB Bit 7 Bit 7
PORT TMR_2, TMR_3
Rev. 3.00 Oct 04, 2005 page 547 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 TCORB _2 TCORB _3 TCNT_2 TCNT_3 SBYCR SYSCR SCKCR MDCR MSTP CRA MSTP CRB MSTP CRC LPWR CR BARA Bit 7 Bit 7 Bit 7 Bit 7 SSBY MACS PSTOP
Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 STS2
Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 STS1 INTM1
Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 STS0 INTM0
Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 NMIEG STCS
Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 SCK2 MDS2
Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 SCK1 MDS1
Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 RAME SCK0 MDS0
Module TMR_2, TMR_3
SYSTEM
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 BAA23 BAA15 BAA7 BAA22 BAA14 BAA6 BAB22 BAB14 BAB6 CDA CDB
IRQ3SCA
BAA21 BAA13 BAA5 BAB21 BAB13 BAB5
BAA20 BAA12 BAA4 BAB20 BAB12 BAB4
BAA19 BAA11 BAA3 BAB19 BAB11 BAB3
BAA18 BAA10 BAA2 BAB18 BAB10 BAB2
STC1 BAA17 BAA9 BAA1 BAB17 BAB9 BAB1 CSELA0 CSELB0
IRQ4SCB IRQ0SCB
STC0 BAA16 BAA8 BAA0 BAB16 BAB8 BAB0 BIEA BIEB
IRQ4SCA IRQ0SCA
PBC
BARB
BAB23 BAB15 BAB7
BCRA BCRB ISCRH ISCRL IER ISR
CMFA CMFB
IRQ3SCB
BAMRA2 BAMRA1 BAMRA0 CSELA1 BAMRB2 BAMRB1 BAMRB0 CSELB1
IRQ2SCB IRQ2SCA IRQ5SCB IRQ1SCB IRQ5SCA IRQ1SCA
INT

IRQ5E IRQ5F
IRQ4E IRQ4F
IRQ3E IRQ3F
IRQ2E IRQ2F
IRQ1E IRQ1F
IRQ0E IRQ0F
Rev. 3.00 Oct 04, 2005 page 548 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 DTCERA DTCEA7 DTCERB DTCEB7
Bit 6 DTCEA6 DTCEB6
Bit 5 DTCEA5 DTCEB5
Bit 4 DTCEA4 DTCEB4
Bit 3 DTCEA3 DTCEB3
Bit 2 DTCEA2 DTCEB2
Bit 1 DTCEA1 DTCEB1
Bit 0 DTCEA0 DTCEB0
Module DTC
DTCERC DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCERD DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCERE DTCEE7 DTCERF DTCEF7 DTCEE6 DTCEF6 DTCEE5 DTCEF5 DTCEE4 DTCEF4 DTCEE3 DTCEF3 DTCEE2 DTCEF2 DTCEE1 DTCEF1 DTCEE0 DTCEF0
DTCERG DTCEG7 DTCEG6 DTCEG5 DTCEG4 DTCEG3 DTCEG2 DTCEG1 DTCEG0 DTVECR SWDTE PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL P1DDR P3DDR P7DDR PADDR PBDDR PCDDR PDDDR PFDDR PAPCR PBPCR PCPCR PDPCR DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 PPG G3INV NDER15 NDER7 POD15 POD7 NDR15 NDR7 P17DDR P37DDR P77DDR G2INV NDER14 NDER6 POD14 POD6 NDR14 NDR6 P16DDR P36DDR P76DDR NDER13 NDER5 POD13 POD5 NDR13 NDR5 P15DDR P35DDR P75DDR NDER12 NDER4 POD12 POD4 NDR12 NDR4 P14DDR P34DDR P74DDR G3NOV NDER11 NDER3 POD11 POD3 NDR11 NDR3 NDR11 NDR3 P13DDR P33DDR P73DDR G2NOV NDER10 NDER2 POD10 POD2 NDR10 NDR2 NDR10 NDR2 P12DDR P32DDR P72DDR NDER9 NDER1 POD9 POD1 NDR9 NDR1 NDR9 NDR1 P11DDR P31DDR P71DDR NDER8 NDER0 POD8 POD0 NDR8 NDR0 NDR8 NDR0 P10DDR P30DDR P70DDR PORT
PA3DDR PA2DDR PA1DDR PA0DDR
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PA3PCR PA2PCR PB3PCR PB2PCR PF1DDR PF0DDR PA1PCR PA0PCR PB1PCR PB0PCR
PB7PCR PB6PCR
PB5PCR PB4PCR
PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR
Rev. 3.00 Oct 04, 2005 page 549 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 P3ODR PAODR PBODR PCODR TCR_3
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module PORT
P37ODR P36ODR
P35ODR P34ODR
P33ODR P32ODR
P31ODR P30ODR
PA3ODR PA2ODR PA1ODR PA0ODR
PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR CCLR2 CCLR1 IOB2 IOD2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 CCLR0 BFB IOB1 IOD1 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPU_4 TPU_3
TMDR_3 TIORH_3 IOB3 TIORL_3 IOD3 TIER_3 TSR_3 TTGE
TCNTH_3 Bit 15 TCNTL_3 Bit 7 TGRAH_3 Bit 15 TGRAL_3 Bit 7 TGRBH_3 Bit 15 TGRBL_3 Bit 7 TGRCH_3 Bit 15 TGRCL_3 Bit 7 TGRDH_3 Bit 15 TGRDL_3 Bit 7 TCR_4
TMDR_4 TIOR_4 TIER_4 TSR_4 IOB3 TTGE TCFD
TCNTH_4 Bit 15 TCNTL_4 Bit 7 TGRAH_4 Bit 15 TGRAL_4 Bit 7 TGRBH_4 Bit 15 TGRBL_4 Bit 7
Rev. 3.00 Oct 04, 2005 page 550 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 TCR_5
Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6
Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CST5 SYNC5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5
Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CST4 SYNC4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4
Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 CST3 SYNC3 RAMS
Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 CST2 SYNC2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 RAM2
Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 CST1 SYNC1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 RAM1
Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 CST0 SYNC0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 RAM0
Module TPU_5
TMDR_5 TIOR_5 TIER_5 TSR_5 IOB3 TTGE TCFD
TCNTH_5 Bit 15 TCNTL_5 Bit 7 TGRAH_5 Bit 15 TGRAL_5 Bit 7 TGRBH_5 Bit 15 TGRBL_5 Bit 7 TSTR TSYR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRM RAMER
TPU common INT
FLASH (F-ZTAT Version) PORT
P1DR P3DR P7DR PADR
P17DR P37DR P77DR
P16DR P36DR P76DR
P15DR P35DR P75DR
P14DR P34DR P74DR
P13DR P33DR P73DR PA3DR
P12DR P32DR P72DR PA2DR
P11DR P31DR P71DR PA1DR
P10DR P30DR P70DR PA0DR
Rev. 3.00 Oct 04, 2005 page 551 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 PBDR PCDR PDDR PFDR TCR_0 PB7DR PC7DR PD7DR PF7DR CCLR2
Bit 6 PB6DR PC6DR PD6DR PF6DR CCLR1 IOB2 IOD2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6
Bit 5 PB5DR PC5DR PD5DR PF5DR CCLR0 BFB IOB1 IOD1 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5
Bit 4 PB4DR PC4DR PD4DR PF4DR CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4
Bit 3 PB3DR PC3DR PD3DR PF3DR CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3
Bit 2 PB2DR PC2DR PD2DR PF2DR TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2
Bit 1 PB1DR PC1DR PD1DR PF1DR TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1
Bit 0 PB0DR PC0DR PD0DR PF0DR TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
Module PORT
TPU_0
TMDR_0 TIORH_0 IOB3 TIORL_0 IOD3 TIER_0 TSR_0 TTGE
TCNTH_0 Bit 15 TCNTL_0 Bit 7 TGRAH_0 Bit 15 TGRAL_0 Bit 7 TGRBH_0 Bit 15 TGRBL_0 Bit 7
TGRCH_0
Bit 15
TGRCL_0 Bit 7
TGRDH_0
Bit 15
TGRDL_0 Bit 7 TCR_1
TPU_1
TMDR_1 TIOR_1 TIER_1 TSR_1 IOB3 TTGE TCFD
TCNTH_1 Bit 15 TCNTL_1 Bit 7 TGRAH_1 Bit 15 TGRAL_1 Bit 7 TGRBH_1 Bit 15 TGRBL_1 Bit 7
Rev. 3.00 Oct 04, 2005 page 552 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 TCR_2
Bit 6 CCLR1 IOB2 Bit 14 Bit 6 Bit 14 Bit 6 Bit 14 Bit 6 CMIEA CMIEA CMFA CMFA Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 Bit 6 WT/IT Bit 6 RSTE CHR (BLK) Bit 6 RIE Bit 6 RDRF
Bit 5 CCLR0 IOB1 TCIEU TCFU Bit 13 Bit 5 Bit 13 Bit 5 Bit 13 Bit 5 OVIE OVIE OVF OVF Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 Bit 5 TME Bit 5 RSTS PE (PE) Bit 5 TE Bit 5 ORER
Bit 4 CKEG1 IOB0 TCIEV TCFV Bit 12 Bit 4 Bit 12 Bit 4 Bit 12 Bit 4 CCLR1 CCLR1 ADTE Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 O/E (O/E) Bit 4 RE Bit 4 FER
Bit 3 CKEG0 MD3 IOA3 Bit 11 Bit 3 Bit 11 Bit 3 Bit 11 Bit 3 CCLR0 CCLR0 OS3 OS3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 STOP (BCP1) Bit 3 MPIE Bit 3 PER
Bit 2 TPSC2 MD2 IOA2 Bit 10 Bit 2 Bit 10 Bit 2 Bit 10 Bit 2 CKS2 CKS2 OS2 OS2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 Bit 2 CKS2 Bit 2 MP (BCP0) Bit 2 TEIE Bit 2 TEND
Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 9 Bit 1 Bit 9 Bit 1 Bit 9 Bit 1 CKS1 CKS1 OS1 OS1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 CKS1 Bit 1 CKS1 (CKS1) Bit 1 CKE1 Bit 1 MPB
Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 CKS0 CKS0 OS0 OS0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 CKS0 Bit 0 CKS0 (CKS0) Bit 0 CKE0 Bit 0 MPBT
Module TPU_2
TMDR_2 TIOR_2 TIER_2 TSR_2 IOB3 TTGE TCFD
TCNTH_2 Bit 15 TCNTL_2 Bit 7 TGRAH_2 Bit 15 TGRAL_2 Bit 7 TGRBH_2 Bit 15 TGRBL_2 Bit 7 TCR_0 TCR_1 TCSR_0 TCSR_1 CMIEB CMIEB CMFB CMFB
TMR_0, TMR_1
TCORA_0 Bit 7 TCORA_1 Bit 7 TCORB_0 Bit 7 TCORB_1 Bit 7 TCNT_0 TCNT_1 TCSR_0 TCNT_0 Bit 7 Bit 7 OVF Bit 7
WDT_0
RSTCSR WOVF SMR_0*1 C/A
(SMR_0 ) (GM) *2
SCI_0
BRR_0 SCR_0 TDR_0
Bit 7 TIE Bit 7
SSR_0*1 TDRE
Rev. 3.00 Oct 04, 2005 page 553 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7
(SSR_0 ) (TDRE) *2
Bit 6 (RDRF) Bit 6 CHR (BLK) Bit 6 RIE Bit 6 RDRF (RDRF) Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 SWE EB6 P16 P36 P46 P76 P96
Bit 5 (ORER) Bit 5 PE (PE) Bit 5 TE Bit 5 ORER (ORER) Bit 5 AD7 AD7 AD7 AD7 ADST ESU1 EB5 P15 P35 P45 P75 P95
Bit 4 (ERS) Bit 4 O/E (O/E) Bit 4 RE Bit 4 FER (ERS) Bit 4 AD6 AD6 AD6 AD6 SCAN PSU1 EB4 P14 P34 P44 P74 P94
Bit 3 (PER) Bit 3 SDIR STOP (BCP1) Bit 3 MPIE Bit 3 PER (PER) Bit 3 SDIR AD5 AD5 AD5 AD5 CH3 CKS1 EV1 EB3 P13 P33 P43 P73 P93
Bit 2 (TEND) Bit 2 SINV MP (BCP0) Bit 2 TEIE Bit 2 TEND (TEND) Bit 2 SINV AD4 AD4 AD4 AD4 CH2 CKS0 PV1 EB2 P12 P32 P42 P72 P92
Bit 1 (MPB) Bit 1 CKS1 (CKS1) Bit 1 CKE1 Bit 1 MPB (MPB) Bit 1 AD3 AD3 AD3 AD3 CH1 E1 EB1 EB9 P11 P31 P41 P71 P91
Bit 0 (MPBT) Bit 0 SMIF CKS0 (CKS0) Bit 0 CKE0 Bit 0 MPBT (MPBT) Bit 0 SMIF AD2 AD2 AD2 AD2 CH0 P1 EB0 EB8 P10 P30 P40 P70 P90
Module SCI_0
RDR_0
Bit 7
SCMR_0
1 SMR_2* C/A
SCI_2
(SMR_2*2) (GM)
BRR_2 SCR_2 TDR_2 SSR_2 *1
Bit 7 TIE Bit 7 TDRE
(SSR_2 ) (TDRE)
*2
RDR_2
Bit 7
SCMR_2 ADDRAH AD9 ADDRAL AD1 ADDRBH AD9 ADDRBL AD1 ADDRCH AD9 ADDRCL AD1 ADDRDH AD9 ADDRDL AD1 ADCSR ADCR ADF TRGS1
A/D
FLMCR1 FWE FLMCR2 FLER EBR1 EBR2 PORT1 PORT3 PORT4 PORT7 PORT9 EB7 P17 P37 P47 P77 P97
FLASH (F-ZTAT Version)
PORT
Rev. 3.00 Oct 04, 2005 page 554 of 598 REJ09B0155-0300
Section 22 List of Registers
Abbreviation Bit 7 PORTA PORTB PORTC PORTD PORTF PB7 PC7 PD7 PF7
Bit 6 PB6 PC6 PD6 PF6
Bit 5 PB5 PC5 PD5 PF5
Bit 4 PB4 PC4 PD4 PF4
Bit 3 PA3 PB3 PC3 PD3 PF3
Bit 2 PA2 PB2 PC2 PD2 PF2
Bit 1 PA1 PB1 PC1 PD1 PF1
Bit 0 PA0 PB0 PC0 PD0 PF0
Module PORT
Notes: 1. Normal serial communication interface mode. 2. Smart Card interface mode. Some bit functions of SMR differ in normal serial communication interface mode and Smart Card interface mode.
Rev. 3.00 Oct 04, 2005 page 555 of 598 REJ09B0155-0300
Section 22 List of Registers
22.3
Register States in Each Operating Mode
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized High Speed Medium Speed Sleep Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Hardware Standby Module Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN
Register Abbreviation MCR GSR BCR MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR MBIMR IMR REC TEC UMSR LAFML LAFMH MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] MC1[1] MC1[2]
Rev. 3.00 Oct 04, 2005 page 556 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation MC1[3] MC1[4] MC1[5] MC1[6] MC1[7] MC1[8] MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] MC3[1] MC3[2] MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] MC4[1] MC4[2] MC4[3] MC4[4] MC4[5] MC4[6] MC4[7] MC4[8] High Speed Medium Speed Module Stop Software Standby Hardware Standby Module HCAN
Reset
Sleep
Rev. 3.00 Oct 04, 2005 page 557 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation MC5[1] MC5[2] MC5[3] MC5[4] MC5[5] MC5[6] MC5[7] MC5[8] MC6[1] MC6[2] MC6[3] MC6[4] MC6[5] MC6[6] MC6[7] MC6[8] MC7[1] MC7[2] MC7[3] MC7[4] MC7[5] MC7[6] MC7[7] MC7[8] MC8[1] MC8[2] MC8[3] MC8[4] MC8[5] MC8[6] High Speed Medium Speed Module Stop Software Standby Hardware Standby Module HCAN
Reset
Sleep
Rev. 3.00 Oct 04, 2005 page 558 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation MC8[7] MC8[8] MC9[1] MC9[2] MC9[3] MC9[4] MC9[5] MC9[6] MC9[7] MC9[8] MC10[1] MC10[2] MC10[3] MC10[4] MC10[5] MC10[6] MC10[7] MC10[8] MC11[1] MC11[2] MC11[3] MC11[4] MC11[5] MC11[6] MC11[7] MC11[8] MC12[1] MC12[2] MC12[3] MC12[4] High Speed Medium Speed Module Stop Software Standby Hardware Standby Module HCAN
Reset
Sleep
Rev. 3.00 Oct 04, 2005 page 559 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation MC12[5] MC12[6] MC12[7] MC12[8] MC13[1] MC13[2] MC13[3] MC13[4] MC13[5] MC13[6] MC13[7] MC13[8] MC14[1] MC14[2] MC14[3] MC14[4] MC14[5] MC14[6] MC14[7] MC14[8] MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] MD0[1] MD0[2] High Speed Medium Speed Module Stop Software Standby Hardware Standby Module HCAN
Reset
Sleep
Rev. 3.00 Oct 04, 2005 page 560 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] MD1[1] MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] MD2[1] MD2[2] MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] High Speed Medium Speed Module Stop Software Standby Hardware Standby Module HCAN
Reset
Sleep
Rev. 3.00 Oct 04, 2005 page 561 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation MD4[1] MD4[2] MD4[3] MD4[4] MD4[5] MD4[6] MD4[7] MD4[8] MD5[1] MD5[2] MD5[3] MD5[4] MD5[5] MD5[6] MD5[7] MD5[8] MD6[1] MD6[2] MD6[3] MD6[4] MD6[5] MD6[6] MD6[7] MD6[8] MD7[1] MD7[2] MD7[3] MD7[4] MD7[5] MD7[6] High Speed Medium Speed Module Stop Software Standby Hardware Standby Module HCAN
Reset
Sleep
Rev. 3.00 Oct 04, 2005 page 562 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation MD7[7] MD7[8] MD8[1] MD8[2] MD8[3] MD8[4] MD8[5] MD8[6] MD8[7] MD8[8] MD9[1] MD9[2] MD9[3] MD9[4] MD9[5] MD9[6] MD9[7] MD9[8] MD10[1] MD10[2] MD10[3] MD10[4] MD10[5] MD10[6] MD10[7] MD10[8] MD11[1] MD11[2] MD11[3] MD11[4] High Speed Medium Speed Module Stop Software Standby Hardware Standby Module HCAN
Reset
Sleep
Rev. 3.00 Oct 04, 2005 page 563 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation MD11[5] MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] MD12[4] MD12[5] MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1] MD14[2] MD14[3] MD14[4] MD14[5] MD14[6] MD14[7] MD14[8] MD15[1] MD15[2] High Speed Medium Speed Module Stop Software Standby Hardware Standby Module HCAN
Reset
Sleep
Rev. 3.00 Oct 04, 2005 page 564 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8] HCANMON SSCRH_0 SSCRL_0 SSMR_0 SSER_0 SSSR_0 SSTDR0_0 SSTDR1_0 SSTDR2_0 SSTDR3_0 SSRDR0_0 SSRDR1_0 SSRDR2_0 SSRDR3_0 SSCRH_1 SSCRL_1 SSMR_1 SSER_1 SSSR_1 SSTDR0_1 SSTDR1_1 SSTDR2_1 SSTDR3_1 SSRDR0_1 High Speed Medium Speed Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Hardware Standby Module Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SSU_1 SSU_0 HCAN
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Sleep
Rev. 3.00 Oct 04, 2005 page 565 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation SSRDR1_1 SSRDR2_1 SSRDR3_1 PDRTIDR TCR_2 TCR_3 TCSR_2 TCSR_3 TCORA_2 TCORA_3 TCORB_2 TCORB_3 TCNT_2 TCNT_3 SBYCR SYSCR SCKCR MDCR MSTPCRA MSTPCRB MSTPCRC LPWRCR BARA BARB BCRA BCRB ISCRH ISCRL IER ISR High Speed Medium Speed Module Stop Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Hardware Standby Module Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized INT PBC SYSTEM PORT TMR_2, TMR_3 SSU_1
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Sleep
Rev. 3.00 Oct 04, 2005 page 566 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTVECR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL P1DDR P3DDR P7DDR PADDR PBDDR PCDDR PDDDR PFDDR PAPCR PBPCR PCPCR PDPCR High Speed Medium Speed Module Stop Software Standby Hardware Standby Module Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PORT PPG DTC
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Sleep
Rev. 3.00 Oct 04, 2005 page 567 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation P3ODR PAODR PBODR PCODR TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNTH_3 TCNTL_3 TGRAH_3 TGRAL_3 TGRBH_3 TGRBL_3 TGRCH_3 TGRCL_3 TGRDH_3 TGRDL_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNTH_4 TCNTL_4 TGRAH_4 TGRAL_4 TGRBH_3 TGRBL_4 High Speed Medium Speed Module Stop Software Standby Hardware Standby Module Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_4 TPU_3 PORT
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Sleep
Rev. 3.00 Oct 04, 2005 page 568 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNTH_5 TCNTL_5 TGRAH_5 TGRAL_5 TGRBH_5 TGRBL_5 TSTR TSYR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRM RAMER P1DR P3DR P7DR PADR PBDR High Speed Medium Speed Module Stop Software Standby Hardware Standby Module Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized ROM PORT TPU common INT TPU_5
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Sleep
Rev. 3.00 Oct 04, 2005 page 569 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation PCDR PDDR PFDR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNTH_0 TCNTL_0 TGRAH_0 TGRAL_0 TGRBH_0 TGRBL_0 TGRCH_0 TGRCL_0 TGRDH_0 TGRDL_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNTH_1 TCNTL_1 TGRAH_1 TGRAL_1 TGRBH_1 TGRBL_1 High Speed Medium Speed Module Stop Software Standby Hardware Standby Module Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_1 TPU_0 PORT
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Sleep
Rev. 3.00 Oct 04, 2005 page 570 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNTH_2 TCNTL_2 TGRAH_2 TGRAL_2 TGRBH_2 TGRBL_2 TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 TCSR_0 TCNT_0 RSTCSR SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 High Speed Medium Speed Module Stop Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Hardware Standby Module Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_0 WDT_0 TMR_0, TMR_1 TPU_2
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Sleep
Rev. 3.00 Oct 04, 2005 page 571 of 598 REJ09B0155-0300
Section 22 List of Registers
Register Abbreviation SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR FLMCR1 FLMCR2 EBR1 EBR2 PORT1 PORT3 PORT4 PORT7 PORT9 PORTA PORTB PORTC PORTD PORTF High Speed Medium Speed Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Hardware Standby Module Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PORT ROM A/D SCI_2
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Sleep
Note: is not initialized. Rev. 3.00 Oct 04, 2005 page 572 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
Section 23 Electrical Characteristics
23.1 Absolute Maximum Ratings
Table 23.1 lists the absolute maximum ratings. Table 23.1 Absolute Maximum Ratings
Item Power supply voltage Input voltage (XTAL, EXTAL) Input voltage (ports 4 and 9) Input voltage (except XTAL, EXTAL, ports 4 and 9) Analog power supply voltage Analog input voltage Operating temperature Symbol VCC Vin Vin Vin AVCC VAN Topr Tstg Value -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to VCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Storage temperature -55 to +125 Unit V V V V V V C C C
Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded.
Rev. 3.00 Oct 04, 2005 page 573 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
23.2
DC Characteristics
Table 23.2 lists the DC characteristics. Table 23.3 lists the permissible output currents. Table 23.2 DC Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1
Item
0QRI 5QRI SER SER
Symbol to VT VT , , NMI, MD2 to MD0, FWE EXTAL Ports 7, 3, 1, A to D, F, HRxD Ports 9 and 4
YBTS YBTS
Min VCC x 0.2
-
Typ
Max VCC x 0.7 VCC + 0.3
Unit V V V V
Test Conditions
Schmitt trigger input voltage Input high voltage
- + +
VT - VT VIH
VCC x 0.05 VCC x 0.9
VCC x 0.7 VCC x 0.7

VCC + 0.3 VCC + 0.3
V V
AVCC x 0.7 VIL -0.3
AVCC + 0.3 V VCC x 0.1 V
Input low voltage
, , NMI, MD2 to MD0, FWE EXTAL Ports 7, 3, 1, A to D, F, HRxD Ports 9, 4
-0.3 -0.3

VCC x 0.2 VCC x 0.2
V V
-0.3 VCC - 0.5 VCC - 1.0

AVCC x 0.2 V 0.4 V V V IOH = -200 A IOH = -1 mA IOL = 1.6 mA
Output high voltage Output low voltage
All output pins VOH All output pins VOL
Rev. 3.00 Oct 04, 2005 page 574 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics Test Conditions Vin = 0.5 to VCC - 0.5 V
Item
SER
Symbol | Iin |
Min
Typ
Max 1.0 1.0
Unit A A
Input leakage current
, NMI, MD2 to MD0, FWE, HRxD
YBTS SER
Ports 9, 4 Input pull-up Ports A to D MOS current Input capacitance -IP Cin
30

1.0 300 30 30 15
A A pF pF pF
Vin = 0.5 to AVCC - 0.5 V Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C
NMI All input pins except and NMI
Current Normal consumption*2 operation Sleep mode All modules stopped
Mediumspeed mode (/32) Standby mode Analog During A/D power supply conversion current Idle Reference During A/D power supply conversion current Idle RAM standby voltage AlCC
Notes: 1. If the A/D converter is not used, do not leave the AVCC, Vref, and AVSS pins open. Apply a voltage between 4.5 V and 5.5 V to the AVCC pin by connecting them to VCC, for instance.
SER
ICC*3

80 90 mA VCC = 5.0 V VCC = 5.5 V 60 70 mA VCC = 5.0 V VCC = 5.5 V 55 mA
f = 24 MHz f = 24 MHz f = 24 MHz, VCC = 5.0 V (reference values) f = 24 MHz, VCC = 5.0 V (reference values) Ta 50C 50C < Ta AVCC = 5.0 V
65
mA
AlCC VRAM 2.0
2.0 1.0 1.0
5.0 200 2.0 5.0 2.0 5.0
A A mA A mA A V
Vref = 5.0 V
Rev. 3.00 Oct 04, 2005 page 575 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics 2. Current consumption values are for VIH = VCC (EXTAL), AVCC (ports 4 and 9), or VCC (other), and VIL = 0 V, with all output pins unloaded and the on-chip pull-up MOS transistors in the off state. 3. ICC depends on VCC and f as follows: ICC (max) = 27 + 0.435 x VCC x f (normal operation) ICC (max) = 27 + 0.3 x VCC x f (sleep mode)
Table 23.3 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*
Item Permissible output low current (per pin) Permissible output low current (total) All output pins Total of all output pins VCC = 4.5 to 5.5 V VCC = 4.5 to 5.5 V VCC = 4.5 to 5.5 V VCC = 4.5 to 5.5 V Symbol Min IOL IOL Typ Max 10 100 2.0 30 Unit mA mA mA mA
Permissible output All output high current (per pin) pins Permissible output high current (total) Total of all output pins
-IOH -IOH
Note: * To protect chip reliability, do not exceed the output current values in table 23.3.
23.3
AC Characteristics
Figure 23.1 shows the test conditions for the AC characteristics.
5V C=30 pF RL= 2.4 k RH=12 k Input/output timing measurement levels * Low level : 0.8 V * High level : 2.0 V
RL LSI output pin C RH
Figure 23.1 Output Load Circuit
Rev. 3.00 Oct 04, 2005 page 576 of 598 REJ09B0155-0300

Section 23 Electrical Characteristics
23.3.1
Clock Timing
Table 23.4 lists the clock timing Table 23.4 Clock Timing Conditions : VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V, = 4 MHz to 24 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Oscillation settling time at reset (crystal) Oscillation settling time in software standby (crystal) External clock output settling delay time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT Min 41.6 8 8 20 8 2 Max 250 13 13 Unit ns ns ns ns ns ms ms ms Figure 23.3 Figure 21.3 Figure 23.3 Test Conditions Figure 23.2
tcyc tCH tCf
tCL
tCr
Figure 23.2 System Clock Timing
Rev. 3.00 Oct 04, 2005 page 577 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
EXTAL tDEXT VCC tDEXT
STBY tOSC1 RES tOSC1
Figure 23.3 Oscillation Settling Timing 23.3.2 Control Signal Timing
Table 23.5 lists the control signal timing. Table 23.5 Control Signal Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V, = 4 MHz to 24 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item setup time pulse width
SER SER QRI QRI QRI
Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW
Min 200 20 150 10 200 150 10 200
Max
Unit ns tcyc ns ns ns ns ns ns
Test Conditions Figure 23.4
NMI setup time NMI hold time NMI pulse width (exiting software standby mode) setup time hold time
Figure 23.5
pulse width (exiting software standby mode)
Rev. 3.00 Oct 04, 2005 page 578 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
tRESS RES tRESW
tRESS
Figure 23.4 Reset Input Timing
tNMIS NMI tNMIW tNMIH
IRQi (i = 5 to 0)
tIRQS
tIRQW tIRQH
IRQ Edge input
tIRQS
IRQ Level input
Figure 23.5 Interrupt Input Timing
Rev. 3.00 Oct 04, 2005 page 579 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
23.3.3
Timing of On-Chip Peripheral Modules
Table 23.6 lists the timing of on-chip peripheral modules. Table 23.6 Timing of On-Chip Peripheral Modules Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 , = 4 MHz to 24 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item I/O port Output data delay time Input data setup time Input data hold time Realtime input port data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width SCI Input clock cycle Single edge Both edges Symbol tPWD tPRS tPRH tRTIPH tTOCD tTICS tTCKS tTCKWH tTCKWL Min 25 25 4 25 25 1.5 2.5 4 6 tSCKW tSCKr tSCKf tTXD tRXS tRXH 0.4 40 40 Max 40 40 0.6 1.5 1.5 40 ns Figure 23.11 tScyc tcyc tcyc Figure 23.10 ns tcyc Figure 23.9 tcyc ns Figure 23.7 Figure 23.8 Unit ns Test Conditions Figure 23.6
Asynchronous tScyc Synchronous
Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous)
Rev. 3.00 Oct 04, 2005 page 580 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics Test Conditions Figure 23.12 Figure 23.13
Item A/D Trigger input setup time converter HCAN* Transmit data delay time Receive data setup time Receive data hold time PPG TMR Pulse output delay time Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Note: * Single edge Both edges
Symbol tTRGS tHTXD tHRXS tHRXH tPOD tTMOD tTMRS tTMCS tTMCWH tTMCWL
Min 30 80 80 25 25 1.5 2.5
Max 80 40 40
Unit ns ns
ns ns ns ns tCYC
Figure 23.14 Figure 23.15 Figure 23.17 Figure 23.16
The HCAN input signal is asynchronous. However, its state is judged to have changed at the rising-edge (two clock cycles) of the clock signal shown in figure 23.13. The HCAN output signal is also asynchronous. Its state changes based on the rising-edge (two clock cycles) of the clock signal shown in figure 23.13.
Rev. 3.00 Oct 04, 2005 page 581 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
Table 23.7 Timing of SSU Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 , = 4 MHz to 24 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item SSU Clock cycle Clock high level pulse width Clock low level pulse width Clock rise time Clock fall time Data input setup time Data input hold time SCS setup time Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Symbol tSUCYC tHI Min 2 4 20 60 20 60 30 30 10 10 1.5 1.5 1.5 1.5 30 30 1.5 1.5 Max 256 256 20 20 40 40 1 1 Unit tCYC ns Test Conditions Figure 23.18 Figure 23.19 Figure 23.20 Figure 23.21
tLO
ns
tRISE tFALL tSU tH tLEAD tLAG tOD tOH tTD
ns ns ns ns tCYC tCYC ns ns tCYC
SCS hold time Master Slave Data output delay time Data output hold time Master Slave Master Slave
Continuous Master transmit delay Slave time Slave access time Slave out release time
tSA tREL
tCYC tCYC
Rev. 3.00 Oct 04, 2005 page 582 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
T1
T2
tPRS Ports 9, 7, 4, 3, 1, A to D, F (read)
tPWD tPRH
Ports 7, 3, 1, A to D, F (write)
Figure 23.6 I/O Port Input/Output Timing
IRQ3 tRTIPH
Port D input
Figure 23.7 Realtime Input Port Data Input Timing
tTOCD Output compare output*
tTICS Input capture input*
Note: * TIOCA5 to TIOCA0, TIOCB5 to TIOCB0, TIOCC3, TIOCC0, TIOCD3, TIOCD0
Figure 23.8 TPU Input/Output Timing
Rev. 3.00 Oct 04, 2005 page 583 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS
Figure 23.9 TPU Clock Input Timing
tSCKW tSCKr
tSCKf
SCK2, SCK0
tScyc
Figure 23.10 SCK Clock Input Timing
SCK2, SCK0
tTXD TxD2, TxD0 (transmit data) tRXS RxD2, RxD0 (receive data) tRXH
Figure 23.11 SCI Input/Output Timing (Clocked Synchronous Mode)
tTRGS ADTRG
Figure 23.12 A/D Converter External Trigger Input Timing
Rev. 3.00 Oct 04, 2005 page 584 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
tHTXD HTxD (transmit data) tHRXS HRxD (receive data) tHRXH
Figure 23.13 HCAN Input/Output Timing
tPOD PO15 to 8
Figure 23.14 PPG Output Timing
tTMOD TMO3, TMO2 TMO1, TMO0
Figure 23.15 8-Bit Timer Output Timing
tTMCS TMCI23, TMCI01 tTMCWL tTMCWH tTMCS
Figure 23.16 8-Bit Timer Clock Input Timing
Rev. 3.00 Oct 04, 2005 page 585 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
tTMRS TMRI23, TMRI01
Figure 23.17 8-Bit Timer Reset Input Timing
SCS (output) tTD tLEAD SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO SSO (output) tOH SSI (input) tSU tH tOD tSUCYC tHI tFALL tRISE tLAG
Figure 23.18 SSU Timing (Master, CPHS = 1)
Rev. 3.00 Oct 04, 2005 page 586 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
SCS (output) tTD tLEAD SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO SSO (output) tOH SSI (input) tSU tH tOD tSUCYC tHI tFALL tRISE tLAG
Figure 23.19 SSU Timing (Master, CPHS = 0)
SCS (input) tLEAD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO SSO (input) tSU SSI (output) tSA tOH tOD tH tSUCYC tHI tFALL tRISE tLAG tTD
tREL
Figure 23.20 SSU Timing (Slave, CPHS = 1)
Rev. 3.00 Oct 04, 2005 page 587 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
SCS (input) tLEAD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO SSO (input) tSU SSI (output) tSA tOH tOD tH tREL tSUCYC tHI tFALL tRISE tLAG tTD
Figure 23.21 SSU Timing (Slave, CPHS = 0)
Rev. 3.00 Oct 04, 2005 page 588 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
23.4
A/D Conversion Characteristics
Table 23.8 lists the A/D conversion characteristics. Table 23.8 A/D Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0V, = 4 MHz to 24 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Min 10 10 Typ 10 0.5 Max 10 200 20 5 3.5 3.5 3.5 4.0 Unit bits s pF k LSB LSB LSB LSB LSB
Rev. 3.00 Oct 04, 2005 page 589 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
23.5
Flash Memory Characteristics
Table 23.9 lists the flash memory characteristics. Table 23.9 Flash Memory Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = 0 to +75C (Programming/erasing operating temperature range)
Item Programming time*1 *2 *4
135 Erase time* * *
Symbol Min tP tE NWEC
1
Typ 10 100 1 50 30 200 10
Max 200 1200 100 32 202 12
Unit ms/ 128 bytes ms/block Times s s s s s
Test Condition
1 50 28 198 8
Reprogramming count Programming Wait time after SWE bit setting * 1 Wait time after PSU1 bit setting *
14 Wait time after P1 bit setting * *
tsswe tspsu tsp30 tsp200 tsp10
Programming time wait Programming time wait Additionalprogramming time wait
Wait time after P1 bit clear *1 Wait time after PSU1 bit clear *1 Wait time after PV1 bit setting *1
tcp tcpsu tspv
5 5 4 2 2 100 1 100 10 10 10 20 2 4 100 12
5 5 4 2 2 100 1 100 10 10 10 20 2 4 100
1000 100 120
s s s s s s Times s s ms s s s s s s Times Erase time wait
Wait time after H'FF dummy write*1 tspvr Wait time after PV1 bit clear *1 tcpv Wait time after SWE bit clear*1 Maximum programming count*1 *4 Erase Wait time after SWE bit setting *1 Wait time after ESU1 bit setting *1 Wait time after E1 bit setting *1 *5 Wait time after E1 bit clear *1 Wait time after ESU1 bit clear *1 Wait time after EV1 bit setting *1 Wait time after H'FF dummy write* 1 Wait time after EV1 bit clear * Wait time after SWE bit clear* Maximum erase count*1 *5
1 1
tcswe N tsswe tsesu tse tce tcesu tsev tsevr tcev tcswe N
Rev. 3.00 Oct 04, 2005 page 590 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (shows the total period for which the P1 bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time.) 3. Block erase time (shows the total period for which the E1-bit FLMCR1 is set. It does not include the erase verification time.) 4. To specify the maximum programming time value (tp (max)) in the 128-bytes programming algorithm, set the max. value (1000) for the maximum programming count (n). The wait time after P1 bit setting should be changed as follows according to the value of the programming counter (n). Programming counter (n) = 1 to 6: tsp30 = 30 s Programming counter (n) = 7 to 1000: tsp200 = 200 s [In additional programming] Programming counter (n) = 1 to 6: tsp10 = 10 s 5. For the maximum erase time (tE (max)), the following relationship applies between the wait time after E1 bit setting (tse) and the maximum erase count (N): tE (max) = Wait time after E1 bit setting (tse) x maximum erase count (N) To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy the above formula. Examples: When tse = 100 ms, N = 12 times When tse = 10 ms, N = 120 times
Rev. 3.00 Oct 04, 2005 page 591 of 598 REJ09B0155-0300
Section 23 Electrical Characteristics
Rev. 3.00 Oct 04, 2005 page 592 of 598 REJ09B0155-0300
Appendix
Appendix
A. I/O Port States in Each Pin State
MCU Operating Mode 7 7 7 7 7 7 7 7 7 7 Hardware Standby Mode T T T T T T T T T T Software Standby Mode Keep Keep T Keep T Keep Keep Keep Keep [DDR = 0] T [DDR = 1] H PF6 PF5 PF4 PF3 PF2 PF1 PF0 HTxD HRxD 7 7 H Input T T H T Output Input 7 T T Keep Program Execution State Sleep Mode I/O port I/O port Input port I/O port Input port I/O port I/O port I/O port I/O port [DDR = 0] T [DDR = 1] Clock output I/O port
Port Name Port 1 Port 3 Port 4 Port 7 Port 9 Port A Port B Port C Port D PF7
Reset T T T T T T T T T T
Legend: H: High level T: High impedance Keep: Input port becomes high-impedance, output port retains state
Rev. 3.00 Oct 04, 2005 page 593 of 598 REJ09B0155-0300
Appendix
B.
Product Code Lineup
Type Name F-ZTAT version Masked ROM version Masked ROM version Standard product Standard product Standard product HD64F2628 HD6432628 HD6432627 Package (Package Code) QFP-100 (FP-100M)
Product Type H8S/2628 H8S/2627
C.
Package Dimensions
The package dimension that is shown in the Renesas Technology Semiconductor Package Data Book has priority.
JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KB-A Previous Code FP-100M/FP-100MV MASS[Typ.] 1.2g
HD
*1
D
NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 51
75
76
50 bp b1
Reference Symbol
Dimension in Millimeters Min Nom 14 14 2.70 15.8 15.8 16.0 16.0 16.2 16.2 3.05 0.00 0.17 0.12 0.22 0.20 0.12 0.17 0.15 0 0.5 0.08 0.10 1.0 1.0 0.4 0.5 1.0 0.6 8 0.22 0.25 0.27 Max
c1
HE
E
c
D E A2
*2
Terminal cross section
ZE
100 26
HD HE A A1 bp
1 ZD
25
b1 c
A2
c
F
c1
A
A1
L L1
e x y ZD ZE L L1
Detail F
e
*3
y
bp
x
M
Figure C.1 FP-100M Package Dimensions
Rev. 3.00 Oct 04, 2005 page 594 of 598 REJ09B0155-0300
Index
Index
16-Bit Timer Pulse Unit (TPU) .............. 167 Buffer Operation.............................. 212 Cascaded Operation......................... 217 Free-running count operation .......... 206 Input Capture................................... 209 periodic count operation .................. 206 Phase Counting Mode ..................... 224 PWM Modes ................................... 219 Synchronous Operation ................... 211 toggle output.................................... 207 Waveform Output by Compare Match ......................................................... 207 8-Bit Timers ........................................... 251 16-Bit Count Mode.......................... 267 Cascaded Connection ...................... 267 Compare-Match Count Mode.......... 267 Pulse Output .................................... 262 TCNT Incrementation Timing......... 263 Toggle output .................................. 271 A/D Converter ........................................ 449 A/D Converter Activation ............... 233 A/D trigger input ............................. 165 Conversion Time ............................. 457 External Trigger............................... 459 Scan Mode....................................... 456 Single Mode .................................... 456 Address Map............................................. 53 Address Space .......................................... 18 Addressing Modes .................................... 39 Absolute Address .............................. 41 Immediate.......................................... 42 Memory Indirect................................ 42 Program-Counter Relative................. 42 Register Direct................................... 40 Register Indirect ................................ 40 Register Indirect with Displacement . 40 Register Indirect with Post-Increment41 Register Indirect with Pre-Decrement 41 Bcc ...................................................... 27, 36 Bit Rate ................................................... 403 break address ...................................... 87, 90 break conditions........................................ 90 Bus Arbitration ......................................... 99 bus cycle ................................................... 95 Bus Masters .............................................. 99 Clock Pulse Generator ............................ 491 Condition Field ......................................... 38 Condition-Code Register (CCR)............... 22 CPU Operating Modes.............................. 14 Advanced Mode................................. 15 Normal Mode..................................... 14 data direction register.............................. 127 data register............................................. 127 Data Transfer Controller......................... 101 Activation by Software .................... 121 Block Transfer Mode....................... 115 Chain Transfer ......................... 117, 123 DTC Vector Table ........................... 109 Normal Mode........................... 113, 122 Register Information........................ 109 Repeat Mode.................................... 114 software activation........................... 118 Software Activation ......................... 124 vector number for the software activation interrupt........................... 107 Effective Address................................ 39, 43 Effective Address Extension..................... 38 Exception Handling .................................. 55 Interrupts............................................ 61 Reset Exception Handling ................. 57 Stack Status........................................ 63 Traces ................................................ 60 Trap Instruction ................................. 62 Extended Control Register (EXR) ............ 21
Rev. 3.00 Oct 04, 2005 page 595 of 598 REJ09B0155-0300
Index
Flash memory ......................................... 467 Flash Memory Boot Mode....................................... 478 Emulation ........................................ 482 Erase/Erase-Verify .......................... 486 erasing units..................................... 472 Program/Program-Verify................. 484 programming units .......................... 472 Programming/Erasing in User Program Mode ............................................... 480 General Registers...................................... 20 HCAN............................................... 97, 371 11 consecutive recessive bits........... 400 Arbitration field....................... 407, 410 buffer segment................................. 403 Configuration mode......................... 400 Control field .................................... 407 Data field ......................................... 407 Data frame ....................................... 410 DTC Interface.................................. 417 HCAN Halt Mode ........................... 415 HCAN Sleep Mode ......................... 412 mailbox............................................ 396 Message Control (MC0 to MC15)... 396 Message Data (MD0 to MD15) ....... 398 Message transmission cancellation.. 407 Message Transmission Method ....... 405 Remote frame .................................. 411 remote transmission request bit ....... 411 Unread message overwrite .............. 411 input pull-up MOS.................................. 127 Instruction Set........................................... 27 Arithmetic Operations Instructions ... 30 Bit Manipulation Instructions............ 34 Block Data Transfer Instructions....... 38 Branch Instructions............................ 36 Data Transfer Instructions ................. 29 Logic Operations Instructions ........... 32 Shift Instructions ............................... 33 System Control Instructions .............. 37
Rev. 3.00 Oct 04, 2005 page 596 of 598 REJ09B0155-0300
Interrupt Control Modes ........................... 78 Interrupt Controller................................... 65 Interrupt Exception Handling Vector Table .................................................................. 74 Interrupt Mask Bit..................................... 22 interrupt mask level .................................. 21 interrupt priority register (IPR)................. 65 Interrupts ADI .................................................. 459 CMIA............................................... 268 CMIB............................................... 268 ERS0/OVR0 .................................... 416 NMI ................................................... 73 OVI .................................................. 268 RM0................................................. 416 RM1................................................. 416 SLE0 ................................................ 416 SWDTEND...................................... 118 TCIU_1............................................ 232 TCIU_2............................................ 232 TCIU_4............................................ 232 TCIU_5............................................ 232 TCIV_0............................................ 232 TCIV_1............................................ 232 TCIV_2............................................ 232 TCIV_3............................................ 232 TCIV_4............................................ 232 TCIV_5............................................ 232 TGIA_0............................................ 232 TGIA_1............................................ 232 TGIA_2............................................ 232 TGIA_3............................................ 232 TGIA_4............................................ 232 TGIA_5............................................ 232 TGIB_0............................................ 232 TGIB_1............................................ 232 TGIB_2............................................ 232 TGIB_3............................................ 232 TGIB_4............................................ 232 TGIB_5............................................ 232
Index
TGIC_0............................................ 232 TGIC_3............................................ 232 TGID_0 ........................................... 232 TGID_3 ........................................... 232 WOVI .............................................. 301 MAC instruction....................................... 51 memory cycle ........................................... 95 Multiply-Accumulate Register (MAC)..... 23 On-Board Programming ......................... 477 open-drain control register...................... 127 Operating Mode Selection ........................ 49 Operation Field......................................... 38 PC Break Controller ................................. 87 Pin Arrangement......................................... 3 PLL Circuit............................................. 497 port register............................................. 127 Program Counter (PC).............................. 21 Program/Erase Protection ....................... 488 Programmable Pulse Generator .............. 275 Non-Overlapping Pulse Output ....... 288 output trigger ................................... 282 Programmer Mode.................................. 489 Register Field............................................ 38 Registers ABACK ....................383, 518, 536, 556 ADCR.......................455, 534, 554, 572 ADCSR.....................453, 534, 554, 572 ADDR.......................452, 534, 554, 572 BARA.........................88, 528, 548, 566 BARB .........................89, 528, 548, 566 BCR..........................377, 518, 536, 556 BCRA .........................89, 528, 548, 566 BCRB .........................90, 528, 548, 566 BRR..........................323, 534, 553, 571 CRA................................................. 105 CRB................................................. 106 DAR................................................. 105 DTCER.....................106, 529, 549, 567 DTVECR..................107, 529, 549, 567 EBR1 ........................475, 534, 554, 572
EBR2 ....................... 476, 534, 554, 572 FLMCR1.................. 473, 534, 554, 572 FLMCR2.................. 475, 534, 554, 572 GSR ......................... 375, 518, 536, 556 HCANMON............. 399, 527, 545, 565 IER............................. 69, 529, 548, 566 IMR.......................... 391, 518, 536, 556 IPR............................. 68, 531, 551, 569 IRR .......................... 386, 518, 536, 556 ISCR .......................... 70, 528, 548, 566 ISR ............................. 72, 529, 548, 566 LAFMH ................... 394, 518, 537, 556 LAFML.................... 394, 518, 537, 556 LPWRCR................. 493, 528, 548, 566 MBCR...................... 379, 518, 536, 556 MBIMR ................... 390, 518, 536, 556 MC........................... 396, 518, 537, 556 MCR ........................ 374, 518, 536, 556 MD........................... 398, 523, 541, 560 MDCR ....................... 50, 528, 548, 566 MRA ................................................ 104 MRB ................................................ 105 MSTPCR ................. 506, 528, 548, 566 NDER ...................... 278, 529, 549, 567 NDR......................... 280, 529, 549, 567 P1DDR .................... 131, 529, 549, 567 P1DR ....................... 132, 531, 551, 569 PADDR.................... 145, 529, 549, 567 PADR....................... 146, 532, 551, 569 PAODR.................... 147, 530, 550, 568 PAPCR .................... 147, 529, 549, 567 PBDDR.................... 149, 529, 549, 567 PBDR....................... 150, 532, 552, 569 PBODR.................... 151, 530, 550, 568 PBPCR..................... 151, 529, 549, 567 PCDDR.................... 154, 529, 549, 567 PCDR....................... 155, 532, 552, 570 PCODR.................... 156, 530, 550, 568 PCPCR..................... 156, 530, 549, 567 PCR.......................... 282, 529, 549, 567
Rev. 3.00 Oct 04, 2005 page 597 of 598 REJ09B0155-0300
Index
PDDDR ....................160, 529, 549, 567 PDDR .......................161, 532, 552, 570 PDPCR .....................162, 530, 549, 567 PFDDR .....................163, 529, 549, 567 PFDR........................164, 532, 552, 570 PMR .........................283, 529, 549, 567 PODR .......................279, 529, 549, 567 PORT1......................132, 534, 554, 572 PORT4......................140, 534, 554, 572 PORT9......................144, 535, 554, 572 PORTA.....................146, 535, 555, 572 PORTB .....................150, 535, 555, 572 PORTC .....................155, 535, 555, 572 PORTD.....................161, 535, 555, 572 PORTF .....................164, 535, 555, 572 RAMER....................476, 531, 551, 569 RDR..........................308, 534, 554, 571 REC ..........................392, 518, 536, 556 RFPR ........................385, 518, 536, 556 RSR ................................................. 308 RSTCSR ...................299, 533, 553, 571 RXPR .......................384, 518, 536, 556 SAR ................................................. 105 SBYCR.....................504, 528, 548, 566 SCKCR.....................492, 528, 548, 566 SCMR.......................322, 534, 554, 571 SCR ..........................313, 534, 553, 571 SMR .........................309, 534, 553, 571 SSR...........................316, 534, 553, 571 SYSCR .......................51, 528, 548, 566 TCNT ......................203, 254, 296, 532, 533, 550, 553, 571
TCNTH............................................ 552 TCOR ...................... 254, 528, 547, 566 TCR ......................... 255, 528, 547, 566 TCSR ....................... 257, 528, 547, 566 TDR ......................... 308, 534, 553, 571 TEC.......................... 392, 518, 536, 556 TGR ......................... 213, 530, 550, 568 TIER ........................ 198, 530, 550, 568 TIOR........................ 181, 530, 550, 568 TMDR...................... 179, 530, 550, 568 TSR.......................... 308, 530, 550, 568 TSTR ....................... 203, 531, 551, 569 TSYR ....................... 204, 531, 551, 569 TXACK ................... 382, 518, 536, 556 TXCR ...................... 381, 518, 536, 556 TXPR....................... 380, 518, 536, 556 UMSR...................... 393, 518, 537, 556 Reset ......................................................... 57 Serial Communication Interface ............. 305 Asynchronous Mode........................ 330 bit rate.............................................. 323 Break................................................ 370 framing error.................................... 337 Mark State........................................ 370 overrun error .................................... 337 parity error ....................................... 337 stack pointer (SP)...................................... 20 Time Quanta (TQ) .................................. 404 Trace Bit ................................................... 21 TRAPA instruction ............................. 42, 62 Watchdog Timer ..................................... 295 Interval Timer Mode........................ 300
Rev. 3.00 Oct 04, 2005 page 598 of 598 REJ09B0155-0300
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2628 Group
Publication Date: 1st Edition, September 2002 Rev.3.00, October 04, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
(c)2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> 2-796-3115, Fax: <82> 2-796-2145
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